11 Commits

Author	SHA1	Message	Date
gdkchan	f35d286c8d	Rename ARegisters to AThreadState	2018-02-18 16:28:07 -03:00
gdkchan	1c44d9f66d	Fix for some SIMD issues	2018-02-18 01:57:33 -03:00
gdkchan	161193e113	CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements	2018-02-17 18:06:11 -03:00
gdkchan	7c314eadcf	Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)	2018-02-15 01:32:25 -03:00
gdkchan	7d11a146c0	Generate CIL for SCVTF (vector), add undefined encodings for some instructions	2018-02-12 00:37:20 -03:00
gdkchan	55743c0cba	Only throw undefined instruction exception at execution, not at translation stage	2018-02-10 14:20:46 -03:00
gdkchan	9063766ed6	Add BRK instruction, fix wrong namespace on one of Am interfaces, and disable Debug/Trace logs by default	2018-02-10 10:24:16 -03:00
gdkchan	ccc9ce1908	Move a few more SIMD instructions to emit CIL directly instead of a method call	2018-02-09 17:14:47 -03:00
gdkchan	6a3aa6cd88	Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions	2018-02-09 00:26:20 -03:00
gdkchan	79f028e410	Add FMADD and FMSUB instructions	2018-02-07 20:07:16 -03:00
gdkchan	b7e1d9930d	aloha	2018-02-04 20:08:20 -03:00