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https://github.com/ryujinx-mirror/ryujinx.git
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* Implement a new JIT for Arm devices * Auto-format * Make a lot of Assembler members read-only * More read-only * Fix more warnings * ObjectDisposedException.ThrowIf * New JIT cache for platforms that enforce W^X, currently unused * Remove unused using * Fix assert * Pass memory manager type around * Safe memory manager mode support + other improvements * Actual safe memory manager mode masking support * PR feedback
106 lines
4.6 KiB
C#
106 lines
4.6 KiB
C#
namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
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{
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static class InstEmitNeonRound
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{
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public static void Vraddhn(CodeGenContext context, uint rd, uint rn, uint rm, uint size)
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{
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InstEmitNeonCommon.EmitVectorBinaryNarrow(context, rd, rn, rm, size, context.Arm64Assembler.Raddhn);
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}
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public static void Vrhadd(CodeGenContext context, uint rd, uint rn, uint rm, bool u, uint size, uint q)
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{
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InstEmitNeonCommon.EmitVectorBinary(context, rd, rn, rm, size, q, u ? context.Arm64Assembler.Urhadd : context.Arm64Assembler.Srhadd, null);
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}
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public static void Vrshl(CodeGenContext context, uint rd, uint rn, uint rm, bool u, uint size, uint q)
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{
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InstEmitNeonCommon.EmitVectorBinary(
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context,
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rd,
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rm,
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rn,
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size,
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q,
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u ? context.Arm64Assembler.UrshlV : context.Arm64Assembler.SrshlV,
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u ? context.Arm64Assembler.UrshlS : context.Arm64Assembler.SrshlS);
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}
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public static void Vrshr(CodeGenContext context, uint rd, uint rm, bool u, uint l, uint imm6, uint q)
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{
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uint size = InstEmitNeonCommon.GetSizeFromImm7(imm6 | (l << 6));
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uint shift = InstEmitNeonShift.GetShiftRight(imm6, size);
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InstEmitNeonCommon.EmitVectorBinaryShift(
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context,
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rd,
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rm,
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shift,
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size,
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q,
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isShl: false,
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u ? context.Arm64Assembler.UrshrV : context.Arm64Assembler.SrshrV,
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u ? context.Arm64Assembler.UrshrS : context.Arm64Assembler.SrshrS);
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}
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public static void Vrshrn(CodeGenContext context, uint rd, uint rm, uint imm6)
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{
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uint size = InstEmitNeonCommon.GetSizeFromImm6(imm6);
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uint shift = InstEmitNeonShift.GetShiftRight(imm6, size);
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InstEmitNeonCommon.EmitVectorBinaryNarrowShift(context, rd, rm, shift, size, isShl: false, context.Arm64Assembler.Rshrn);
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}
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public static void Vrsra(CodeGenContext context, uint rd, uint rm, bool u, uint l, uint imm6, uint q)
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{
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uint size = InstEmitNeonCommon.GetSizeFromImm7(imm6 | (l << 6));
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uint shift = InstEmitNeonShift.GetShiftRight(imm6, size);
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InstEmitNeonCommon.EmitVectorTernaryRdShift(
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context,
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rd,
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rm,
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shift,
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size,
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q,
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isShl: false,
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u ? context.Arm64Assembler.UrsraV : context.Arm64Assembler.SrsraV,
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u ? context.Arm64Assembler.UrsraS : context.Arm64Assembler.SrsraS);
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}
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public static void Vrsubhn(CodeGenContext context, uint rd, uint rn, uint rm, uint size)
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{
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InstEmitNeonCommon.EmitVectorBinaryNarrow(context, rd, rn, rm, size, context.Arm64Assembler.Rsubhn);
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}
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public static void Vrinta(CodeGenContext context, uint rd, uint rm, uint size, uint q)
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{
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InstEmitNeonCommon.EmitVectorUnaryAnyF(context, rd, rm, size, q, context.Arm64Assembler.FrintaSingleAndDouble, context.Arm64Assembler.FrintaHalf);
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}
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public static void Vrintm(CodeGenContext context, uint rd, uint rm, uint size, uint q)
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{
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InstEmitNeonCommon.EmitVectorUnaryAnyF(context, rd, rm, size, q, context.Arm64Assembler.FrintmSingleAndDouble, context.Arm64Assembler.FrintmHalf);
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}
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public static void Vrintn(CodeGenContext context, uint rd, uint rm, uint size, uint q)
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{
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InstEmitNeonCommon.EmitVectorUnaryAnyF(context, rd, rm, size, q, context.Arm64Assembler.FrintnSingleAndDouble, context.Arm64Assembler.FrintnHalf);
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}
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public static void Vrintp(CodeGenContext context, uint rd, uint rm, uint size, uint q)
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{
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InstEmitNeonCommon.EmitVectorUnaryAnyF(context, rd, rm, size, q, context.Arm64Assembler.FrintpSingleAndDouble, context.Arm64Assembler.FrintpHalf);
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}
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public static void Vrintx(CodeGenContext context, uint rd, uint rm, uint size, uint q)
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{
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InstEmitNeonCommon.EmitVectorUnaryAnyF(context, rd, rm, size, q, context.Arm64Assembler.FrintxSingleAndDouble, context.Arm64Assembler.FrintxHalf);
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}
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public static void Vrintz(CodeGenContext context, uint rd, uint rm, uint size, uint q)
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{
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InstEmitNeonCommon.EmitVectorUnaryAnyF(context, rd, rm, size, q, context.Arm64Assembler.FrintzSingleAndDouble, context.Arm64Assembler.FrintzHalf);
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}
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}
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}
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