ryujinx/Ryujinx/Cpu
2018-02-14 19:01:21 -03:00
..
Decoder Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
Exceptions Fixes to memory management 2018-02-09 21:13:18 -03:00
Instruction AInstEmitAluHelper: Simplify EmitSubsCCheck (#15) 2018-02-14 19:01:21 -03:00
Memory Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments 2018-02-13 23:43:08 -03:00
State Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
Translation Support loading NSO/NRO without a MOD0 header, stub some functions, support more ids on SvcGetInfo 2018-02-06 20:28:32 -03:00
ABitUtils.cs aloha 2018-02-04 20:08:20 -03:00
AOpCodeTable.cs Add SHRN instruction, and fix ADDV 2018-02-14 02:43:21 -03:00
AOptimizations.cs Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions 2018-02-09 00:26:20 -03:00
AThread.cs Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments 2018-02-13 23:43:08 -03:00
ATranslatedSub.cs aloha 2018-02-04 20:08:20 -03:00
ATranslator.cs aloha 2018-02-04 20:08:20 -03:00