ryujinx/Ryujinx/Cpu/Instruction
2018-02-15 01:35:44 -03:00
..
AInst.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitAlu.cs Add ADC and SBC instructions 2018-02-07 20:46:36 -03:00
AInstEmitAluHelper.cs Shouldn't have undone this 2018-02-15 01:35:44 -03:00
AInstEmitBfm.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitCcmp.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitCsel.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitException.cs Generate CIL for SCVTF (vector), add undefined encodings for some instructions 2018-02-12 00:37:20 -03:00
AInstEmitFlow.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMemory.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMemoryEx.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMemoryHelper.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMove.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitMul.cs aloha 2018-02-04 20:08:20 -03:00
AInstEmitScalar.cs Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
AInstEmitSimd.cs Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
AInstEmitSystem.cs Improve access to system registers by using properties, also use exclusive region granularity on exclusive load/stores, and ensure that acquires without releases won't hold the address forever, remove unused ALU rev method 2018-02-06 12:15:08 -03:00
AInstEmitter.cs aloha 2018-02-04 20:08:20 -03:00
ASoftFallback.cs Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00