2018-12-20 14:09:21 -08:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cstring>
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#include <set>
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#include <fmt/format.h>
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2018-12-20 22:18:54 -08:00
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#include "common/assert.h"
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2018-12-20 14:09:21 -08:00
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/engines/shader_header.h"
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2019-06-04 18:44:06 -07:00
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#include "video_core/shader/node_helper.h"
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2018-12-20 14:09:21 -08:00
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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2018-12-20 22:39:46 -08:00
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namespace {
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2018-12-20 14:09:21 -08:00
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/// Merges exit method of two parallel branches.
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constexpr ExitMethod ParallelExit(ExitMethod a, ExitMethod b) {
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if (a == ExitMethod::Undetermined) {
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return b;
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}
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if (b == ExitMethod::Undetermined) {
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return a;
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}
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if (a == b) {
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return a;
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}
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return ExitMethod::Conditional;
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}
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/**
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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*/
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constexpr bool IsSchedInstruction(u32 offset, u32 main_offset) {
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constexpr u32 SchedPeriod = 4;
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u32 absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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2018-12-20 22:39:46 -08:00
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} // namespace
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2018-12-20 14:09:21 -08:00
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void ShaderIR::Decode() {
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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std::set<u32> labels;
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const ExitMethod exit_method = Scan(main_offset, MAX_PROGRAM_LENGTH, labels);
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if (exit_method != ExitMethod::AlwaysEnd) {
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UNREACHABLE_MSG("Program does not always end");
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}
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if (labels.empty()) {
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basic_blocks.insert({main_offset, DecodeRange(main_offset, MAX_PROGRAM_LENGTH)});
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return;
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}
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labels.insert(main_offset);
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for (const u32 label : labels) {
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const auto next_it = labels.lower_bound(label + 1);
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const u32 next_label = next_it == labels.end() ? MAX_PROGRAM_LENGTH : *next_it;
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basic_blocks.insert({label, DecodeRange(label, next_label)});
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}
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}
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ExitMethod ShaderIR::Scan(u32 begin, u32 end, std::set<u32>& labels) {
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const auto [iter, inserted] =
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exit_method_map.emplace(std::make_pair(begin, end), ExitMethod::Undetermined);
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ExitMethod& exit_method = iter->second;
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if (!inserted)
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return exit_method;
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for (u32 offset = begin; offset != end && offset != MAX_PROGRAM_LENGTH; ++offset) {
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coverage_begin = std::min(coverage_begin, offset);
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coverage_end = std::max(coverage_end, offset + 1);
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const Instruction instr = {program_code[offset]};
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const auto opcode = OpCode::Decode(instr);
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if (!opcode)
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continue;
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switch (opcode->get().GetId()) {
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case OpCode::Id::EXIT: {
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// The EXIT instruction can be predicated, which means that the shader can conditionally
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// end on this instruction. We have to consider the case where the condition is not met
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// and check the exit method of that other basic block.
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using Tegra::Shader::Pred;
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if (instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex)) {
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return exit_method = ExitMethod::AlwaysEnd;
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} else {
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const ExitMethod not_met = Scan(offset + 1, end, labels);
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return exit_method = ParallelExit(ExitMethod::AlwaysEnd, not_met);
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}
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}
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case OpCode::Id::BRA: {
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const u32 target = offset + instr.bra.GetBranchTarget();
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labels.insert(target);
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const ExitMethod no_jmp = Scan(offset + 1, end, labels);
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const ExitMethod jmp = Scan(target, end, labels);
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return exit_method = ParallelExit(no_jmp, jmp);
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}
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case OpCode::Id::SSY:
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case OpCode::Id::PBK: {
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// The SSY and PBK use a similar encoding as the BRA instruction.
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UNIMPLEMENTED_IF_MSG(instr.bra.constant_buffer != 0,
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"Constant buffer branching is not supported");
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const u32 target = offset + instr.bra.GetBranchTarget();
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labels.insert(target);
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// Continue scanning for an exit method.
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break;
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}
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2019-04-03 00:33:36 -07:00
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default:
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break;
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2018-12-20 14:09:21 -08:00
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}
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}
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return exit_method = ExitMethod::AlwaysReturn;
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}
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2019-01-29 21:09:40 -08:00
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NodeBlock ShaderIR::DecodeRange(u32 begin, u32 end) {
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NodeBlock basic_block;
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2018-12-20 14:09:21 -08:00
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for (u32 pc = begin; pc < (begin > end ? MAX_PROGRAM_LENGTH : end);) {
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pc = DecodeInstr(basic_block, pc);
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}
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2019-01-28 04:43:19 -08:00
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return basic_block;
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2018-12-20 14:09:21 -08:00
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}
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2019-01-29 21:09:40 -08:00
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u32 ShaderIR::DecodeInstr(NodeBlock& bb, u32 pc) {
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2018-12-20 14:09:21 -08:00
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// Ignore sched instructions when generating code.
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if (IsSchedInstruction(pc, main_offset)) {
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return pc + 1;
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}
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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// Decoding failure
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if (!opcode) {
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UNIMPLEMENTED_MSG("Unhandled instruction: {0:x}", instr.value);
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return pc + 1;
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}
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bb.push_back(
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Comment(fmt::format("{}: {} (0x{:016x})", pc, opcode->get().GetName(), instr.value)));
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using Tegra::Shader::Pred;
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UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute,
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"NeverExecute predicate not implemented");
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2019-01-29 21:09:40 -08:00
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static const std::map<OpCode::Type, u32 (ShaderIR::*)(NodeBlock&, u32)> decoders = {
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{OpCode::Type::Arithmetic, &ShaderIR::DecodeArithmetic},
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{OpCode::Type::ArithmeticImmediate, &ShaderIR::DecodeArithmeticImmediate},
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{OpCode::Type::Bfe, &ShaderIR::DecodeBfe},
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{OpCode::Type::Bfi, &ShaderIR::DecodeBfi},
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{OpCode::Type::Shift, &ShaderIR::DecodeShift},
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{OpCode::Type::ArithmeticInteger, &ShaderIR::DecodeArithmeticInteger},
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{OpCode::Type::ArithmeticIntegerImmediate, &ShaderIR::DecodeArithmeticIntegerImmediate},
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{OpCode::Type::ArithmeticHalf, &ShaderIR::DecodeArithmeticHalf},
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{OpCode::Type::ArithmeticHalfImmediate, &ShaderIR::DecodeArithmeticHalfImmediate},
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{OpCode::Type::Ffma, &ShaderIR::DecodeFfma},
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{OpCode::Type::Hfma2, &ShaderIR::DecodeHfma2},
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{OpCode::Type::Conversion, &ShaderIR::DecodeConversion},
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{OpCode::Type::Memory, &ShaderIR::DecodeMemory},
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2019-02-21 21:19:45 -08:00
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{OpCode::Type::Texture, &ShaderIR::DecodeTexture},
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{OpCode::Type::FloatSetPredicate, &ShaderIR::DecodeFloatSetPredicate},
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{OpCode::Type::IntegerSetPredicate, &ShaderIR::DecodeIntegerSetPredicate},
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{OpCode::Type::HalfSetPredicate, &ShaderIR::DecodeHalfSetPredicate},
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{OpCode::Type::PredicateSetRegister, &ShaderIR::DecodePredicateSetRegister},
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{OpCode::Type::PredicateSetPredicate, &ShaderIR::DecodePredicateSetPredicate},
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{OpCode::Type::RegisterSetPredicate, &ShaderIR::DecodeRegisterSetPredicate},
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{OpCode::Type::FloatSet, &ShaderIR::DecodeFloatSet},
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{OpCode::Type::IntegerSet, &ShaderIR::DecodeIntegerSet},
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{OpCode::Type::HalfSet, &ShaderIR::DecodeHalfSet},
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{OpCode::Type::Video, &ShaderIR::DecodeVideo},
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{OpCode::Type::Xmad, &ShaderIR::DecodeXmad},
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};
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2018-12-28 15:00:36 -08:00
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std::vector<Node> tmp_block;
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2018-12-20 14:09:21 -08:00
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if (const auto decoder = decoders.find(opcode->get().GetType()); decoder != decoders.end()) {
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2019-01-29 20:56:33 -08:00
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pc = (this->*decoder->second)(tmp_block, pc);
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2018-12-20 14:09:21 -08:00
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} else {
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2019-01-29 20:56:33 -08:00
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pc = DecodeOther(tmp_block, pc);
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2018-12-20 14:09:21 -08:00
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}
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// Some instructions (like SSY) don't have a predicate field, they are always unconditionally
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// executed.
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const bool can_be_predicated = OpCode::IsPredicatedInstruction(opcode->get().GetId());
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const auto pred_index = static_cast<u32>(instr.pred.pred_index);
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if (can_be_predicated && pred_index != static_cast<u32>(Pred::UnusedIndex)) {
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2019-01-29 20:56:33 -08:00
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const Node conditional =
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Conditional(GetPredicate(pred_index, instr.negate_pred != 0), std::move(tmp_block));
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global_code.push_back(conditional);
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bb.push_back(conditional);
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2018-12-20 14:09:21 -08:00
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} else {
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2018-12-28 15:00:36 -08:00
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for (auto& node : tmp_block) {
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global_code.push_back(node);
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bb.push_back(node);
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2018-12-20 14:09:21 -08:00
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}
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}
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return pc + 1;
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}
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2019-04-03 00:33:36 -07:00
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} // namespace VideoCommon::Shader
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