2014-04-15 21:03:41 -07:00
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// Copyright 2014 Citra Emulator Project
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2014-12-16 21:38:14 -08:00
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// Licensed under GPLv2 or any later version
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2014-04-15 21:03:41 -07:00
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// Refer to the license.txt file included.
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2014-05-07 18:04:55 -07:00
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#include "common/bit_field.h"
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2014-04-15 21:03:41 -07:00
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2014-04-25 22:48:24 -07:00
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#include "core/mem_map.h"
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2015-05-12 18:38:29 -07:00
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#include "core/memory.h"
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2014-06-01 07:41:23 -07:00
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#include "core/hle/kernel/event.h"
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2014-07-04 21:59:58 -07:00
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#include "core/hle/kernel/shared_memory.h"
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2015-03-05 19:38:23 -08:00
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#include "core/hle/result.h"
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2014-10-28 20:08:37 -07:00
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#include "gsp_gpu.h"
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2015-03-05 19:38:23 -08:00
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#include "core/hw/hw.h"
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2014-05-17 13:50:33 -07:00
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#include "core/hw/gpu.h"
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2014-10-12 22:40:26 -07:00
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#include "core/hw/lcd.h"
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2014-04-25 22:48:24 -07:00
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2014-05-17 13:26:45 -07:00
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#include "video_core/gpu_debugger.h"
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2014-05-17 13:34:55 -07:00
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// Main graphics debugger object - TODO: Here is probably not the best place for this
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GraphicsDebugger g_debugger;
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2014-10-12 22:40:26 -07:00
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// Beginning address of HW regs
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const static u32 REGS_BEGIN = 0x1EB00000;
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2014-07-04 21:59:58 -07:00
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Namespace GSP_GPU
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namespace GSP_GPU {
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2015-01-22 21:11:25 -08:00
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/// Event triggered when GSP interrupt has been signalled
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Kernel::SharedPtr<Kernel::Event> g_interrupt_event;
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/// GSP shared memoryings
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Kernel::SharedPtr<Kernel::SharedMemory> g_shared_memory;
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/// Thread index into interrupt relay queue
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u32 g_thread_id = 0;
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2014-07-22 21:10:37 -07:00
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/// Gets a pointer to a thread command buffer in GSP shared memory
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static inline u8* GetCommandBuffer(u32 thread_id) {
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return g_shared_memory->GetPointer(0x800 + (thread_id * sizeof(CommandBuffer)));
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2014-05-07 18:04:55 -07:00
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}
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2014-08-19 11:57:43 -07:00
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static inline FrameBufferUpdate* GetFrameBufferInfo(u32 thread_id, u32 screen_index) {
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2015-01-20 17:16:47 -08:00
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DEBUG_ASSERT_MSG(screen_index < 2, "Invalid screen index");
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2014-08-19 11:57:43 -07:00
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// For each thread there are two FrameBufferUpdate fields
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u32 offset = 0x200 + (2 * thread_id + screen_index) * sizeof(FrameBufferUpdate);
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u8* ptr = g_shared_memory->GetPointer(offset);
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return reinterpret_cast<FrameBufferUpdate*>(ptr);
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}
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2014-07-22 21:10:37 -07:00
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/// Gets a pointer to the interrupt relay queue for a given thread index
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static inline InterruptRelayQueue* GetInterruptRelayQueue(u32 thread_id) {
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u8* ptr = g_shared_memory->GetPointer(sizeof(InterruptRelayQueue) * thread_id);
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return reinterpret_cast<InterruptRelayQueue*>(ptr);
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2014-07-22 19:59:26 -07:00
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}
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2015-02-10 18:07:59 -08:00
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/**
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* Checks if the parameters in a register write call are valid and logs in the case that
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* they are not
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* @param base_address The first address in the sequence of registers that will be written
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* @param size_in_bytes The number of registers that will be written
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* @return true if the parameters are valid, false otherwise
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*/
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static bool CheckWriteParameters(u32 base_address, u32 size_in_bytes) {
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// TODO: Return proper error codes
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if (base_address + size_in_bytes >= 0x420000) {
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LOG_ERROR(Service_GSP, "Write address out of range! (address=0x%08x, size=0x%08x)",
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base_address, size_in_bytes);
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return false;
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}
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// size should be word-aligned
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2014-07-25 02:22:40 -07:00
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if ((size_in_bytes % 4) != 0) {
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LOG_ERROR(Service_GSP, "Invalid size 0x%08x", size_in_bytes);
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return false;
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}
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2015-02-10 18:07:59 -08:00
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return true;
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}
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/**
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* Writes sequential GSP GPU hardware registers using an array of source data
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*
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* @param base_address The address of the first register in the sequence
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* @param size_in_bytes The number of registers to update (size of data)
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* @param data A pointer to the source data
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*/
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static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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// TODO: Return proper error codes
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if (!CheckWriteParameters(base_address, size_in_bytes))
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return;
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2014-07-25 02:22:40 -07:00
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while (size_in_bytes > 0) {
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2014-10-12 22:40:26 -07:00
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HW::Write<u32>(base_address + REGS_BEGIN, *data);
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2014-06-01 04:58:14 -07:00
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2014-07-25 02:22:40 -07:00
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size_in_bytes -= 4;
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++data;
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base_address += 4;
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2014-06-01 04:58:14 -07:00
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}
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}
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2015-02-10 18:07:59 -08:00
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/**
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* GSP_GPU::WriteHWRegs service function
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*
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* Writes sequential GSP GPU hardware registers
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*
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* Inputs:
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* 1 : address of first GPU register
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* 2 : number of registers to write sequentially
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* 4 : pointer to source data array
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*/
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2014-11-16 19:58:39 -08:00
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static void WriteHWRegs(Service::Interface* self) {
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2014-12-13 21:30:11 -08:00
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u32* cmd_buff = Kernel::GetCommandBuffer();
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2014-07-25 02:22:40 -07:00
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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2015-02-10 18:07:59 -08:00
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u32* src = (u32*)Memory::GetPointer(cmd_buff[4]);
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2014-07-25 02:22:40 -07:00
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WriteHWRegs(reg_addr, size, src);
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}
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2015-02-10 18:07:59 -08:00
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/**
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* Updates sequential GSP GPU hardware registers using parallel arrays of source data and masks.
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* For each register, the value is updated only where the mask is high
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*
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* @param base_address The address of the first register in the sequence
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* @param size_in_bytes The number of registers to update (size of data)
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* @param data A pointer to the source data to use for updates
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* @param masks A pointer to the masks
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*/
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static void WriteHWRegsWithMask(u32 base_address, u32 size_in_bytes, const u32* data, const u32* masks) {
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// TODO: Return proper error codes
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if (!CheckWriteParameters(base_address, size_in_bytes))
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return;
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while (size_in_bytes > 0) {
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2014-10-12 22:40:26 -07:00
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const u32 reg_address = base_address + REGS_BEGIN;
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u32 reg_value;
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2015-03-05 19:38:23 -08:00
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HW::Read<u32>(reg_value, reg_address);
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2015-02-10 18:07:59 -08:00
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// Update the current value of the register only for set mask bits
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reg_value = (reg_value & ~*masks) | (*data | *masks);
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2015-03-05 19:38:23 -08:00
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HW::Write<u32>(reg_address, reg_value);
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2015-02-10 18:07:59 -08:00
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size_in_bytes -= 4;
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++data;
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++masks;
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base_address += 4;
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}
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}
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/**
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* GSP_GPU::WriteHWRegsWithMask service function
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*
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* Updates sequential GSP GPU hardware registers using masks
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*
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* Inputs:
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* 1 : address of first GPU register
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* 2 : number of registers to update sequentially
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* 4 : pointer to source data array
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* 6 : pointer to mask array
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*/
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static void WriteHWRegsWithMask(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32* src_data = (u32*)Memory::GetPointer(cmd_buff[4]);
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u32* mask_data = (u32*)Memory::GetPointer(cmd_buff[6]);
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WriteHWRegsWithMask(reg_addr, size, src_data, mask_data);
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}
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2014-04-25 22:48:24 -07:00
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/// Read a GSP GPU hardware register
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2014-11-16 19:58:39 -08:00
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static void ReadHWRegs(Service::Interface* self) {
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2014-12-13 21:30:11 -08:00
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u32* cmd_buff = Kernel::GetCommandBuffer();
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2014-04-25 22:48:24 -07:00
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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2014-05-17 13:26:45 -07:00
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2014-06-01 04:58:14 -07:00
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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2014-12-05 17:53:49 -08:00
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LOG_ERROR(Service_GSP, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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2014-06-01 04:58:14 -07:00
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return;
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}
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2014-04-25 22:48:24 -07:00
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2014-06-01 04:58:14 -07:00
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// size should be word-aligned
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if ((size % 4) != 0) {
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2014-12-05 17:53:49 -08:00
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LOG_ERROR(Service_GSP, "Invalid size 0x%08x", size);
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2014-06-01 04:58:14 -07:00
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return;
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}
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2014-04-27 09:41:25 -07:00
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2014-06-01 04:58:14 -07:00
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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2014-04-25 22:48:24 -07:00
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2014-06-01 04:58:14 -07:00
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while (size > 0) {
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2014-10-12 22:40:26 -07:00
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HW::Read<u32>(*dst, reg_addr + REGS_BEGIN);
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2014-04-25 22:48:24 -07:00
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2014-06-01 04:58:14 -07:00
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size -= 4;
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++dst;
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reg_addr += 4;
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2014-04-25 22:48:24 -07:00
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}
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}
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2014-11-16 19:58:39 -08:00
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static void SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
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2014-07-25 02:23:28 -07:00
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u32 base_address = 0x400000;
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2015-02-08 05:38:00 -08:00
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PAddr phys_address_left = Memory::VirtualToPhysicalAddress(info.address_left);
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PAddr phys_address_right = Memory::VirtualToPhysicalAddress(info.address_right);
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2014-07-25 02:23:28 -07:00
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if (info.active_fb == 0) {
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2015-02-01 12:31:21 -08:00
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left1)), 4,
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2015-02-08 05:38:00 -08:00
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&phys_address_left);
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2015-02-01 12:31:21 -08:00
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right1)), 4,
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2015-02-08 05:38:00 -08:00
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&phys_address_right);
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2014-07-25 02:23:28 -07:00
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} else {
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2015-02-01 12:31:21 -08:00
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_left2)), 4,
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2015-02-08 05:38:00 -08:00
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&phys_address_left);
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2015-02-01 12:31:21 -08:00
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].address_right2)), 4,
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2015-02-08 05:38:00 -08:00
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&phys_address_right);
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2014-07-25 02:23:28 -07:00
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}
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2015-02-01 12:31:21 -08:00
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].stride)), 4,
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&info.stride);
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].color_format)), 4,
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&info.format);
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WriteHWRegs(base_address + 4 * static_cast<u32>(GPU_REG_INDEX(framebuffer_config[screen_id].active_fb)), 4,
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&info.shown_fb);
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2014-07-25 02:23:28 -07:00
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}
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/**
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* GSP_GPU::SetBufferSwap service function
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*
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* Updates GPU display framebuffer configuration using the specified parameters.
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*
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* Inputs:
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* 1 : Screen ID (0 = top screen, 1 = bottom screen)
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* 2-7 : FrameBufferInfo structure
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* Outputs:
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* 1: Result code
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*/
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2014-11-16 19:58:39 -08:00
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static void SetBufferSwap(Service::Interface* self) {
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2014-12-13 21:30:11 -08:00
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u32* cmd_buff = Kernel::GetCommandBuffer();
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2014-07-25 02:23:28 -07:00
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u32 screen_id = cmd_buff[1];
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FrameBufferInfo* fb_info = (FrameBufferInfo*)&cmd_buff[2];
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SetBufferSwap(screen_id, *fb_info);
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cmd_buff[1] = 0; // No error
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}
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2014-12-17 21:35:12 -08:00
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/**
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* GSP_GPU::FlushDataCache service function
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*
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* This Function is a no-op, We aren't emulating the CPU cache any time soon.
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*
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* Inputs:
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* 1 : Address
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* 2 : Size
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* 3 : Value 0, some descriptor for the KProcess Handle
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* 4 : KProcess handle
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* Outputs:
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* 1 : Result of function, 0 on success, otherwise error code
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*/
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static void FlushDataCache(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 address = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32 process = cmd_buff[4];
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// TODO(purpasmart96): Verify return header on HW
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cmd_buff[1] = RESULT_SUCCESS.raw; // No error
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2015-03-07 17:54:16 -08:00
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LOG_DEBUG(Service_GSP, "(STUBBED) called address=0x%08X, size=0x%08X, process=0x%08X",
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address, size, process);
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2014-12-17 21:35:12 -08:00
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}
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2014-07-04 21:59:58 -07:00
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/**
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* GSP_GPU::RegisterInterruptRelayQueue service function
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* Inputs:
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* 1 : "Flags" field, purpose is unknown
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* 3 : Handle to GSP synchronization event
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* Outputs:
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2015-05-10 15:51:37 -07:00
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* 1 : Result of function, 0x2A07 on success, otherwise error code
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2014-07-04 21:59:58 -07:00
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* 2 : Thread index into GSP command buffer
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|
|
|
* 4 : Handle to GSP shared memory
|
|
|
|
*/
|
2014-11-16 19:58:39 -08:00
|
|
|
static void RegisterInterruptRelayQueue(Service::Interface* self) {
|
2014-12-13 21:30:11 -08:00
|
|
|
u32* cmd_buff = Kernel::GetCommandBuffer();
|
2014-04-24 19:20:13 -07:00
|
|
|
u32 flags = cmd_buff[1];
|
2014-06-01 07:41:23 -07:00
|
|
|
|
2015-01-22 21:11:25 -08:00
|
|
|
g_interrupt_event = Kernel::g_handle_table.Get<Kernel::Event>(cmd_buff[3]);
|
2015-01-20 17:16:47 -08:00
|
|
|
ASSERT_MSG((g_interrupt_event != nullptr), "handle is not valid!");
|
2015-05-10 15:47:07 -07:00
|
|
|
|
2015-01-10 21:43:29 -08:00
|
|
|
Handle shmem_handle = Kernel::g_handle_table.Create(g_shared_memory).MoveFrom();
|
|
|
|
|
2015-05-10 15:51:37 -07:00
|
|
|
// This specific code is required for a successful initialization, rather than 0
|
|
|
|
cmd_buff[1] = ResultCode((ErrorDescription)519, ErrorModule::GX,
|
|
|
|
ErrorSummary::Success, ErrorLevel::Success).raw;
|
2014-12-02 22:06:09 -08:00
|
|
|
cmd_buff[2] = g_thread_id++; // Thread ID
|
2015-01-10 21:43:29 -08:00
|
|
|
cmd_buff[4] = shmem_handle; // GSP shared memory
|
2014-06-01 07:41:23 -07:00
|
|
|
|
2015-01-22 21:11:25 -08:00
|
|
|
g_interrupt_event->Signal(); // TODO(bunnei): Is this correct?
|
2014-05-07 18:04:55 -07:00
|
|
|
}
|
|
|
|
|
2014-07-22 19:59:26 -07:00
|
|
|
/**
|
|
|
|
* Signals that the specified interrupt type has occurred to userland code
|
|
|
|
* @param interrupt_id ID of interrupt that is being signalled
|
2014-08-19 11:57:43 -07:00
|
|
|
* @todo This should probably take a thread_id parameter and only signal this thread?
|
2014-12-02 22:04:22 -08:00
|
|
|
* @todo This probably does not belong in the GSP module, instead move to video_core
|
2014-07-22 19:59:26 -07:00
|
|
|
*/
|
2014-07-22 20:26:28 -07:00
|
|
|
void SignalInterrupt(InterruptId interrupt_id) {
|
2014-07-22 21:10:37 -07:00
|
|
|
if (0 == g_interrupt_event) {
|
2014-12-05 17:53:49 -08:00
|
|
|
LOG_WARNING(Service_GSP, "cannot synchronize until GSP event has been created!");
|
2014-07-22 19:59:26 -07:00
|
|
|
return;
|
|
|
|
}
|
2015-01-10 21:43:29 -08:00
|
|
|
if (nullptr == g_shared_memory) {
|
2014-12-05 17:53:49 -08:00
|
|
|
LOG_WARNING(Service_GSP, "cannot synchronize until GSP shared memory has been created!");
|
2014-07-22 19:59:26 -07:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
for (int thread_id = 0; thread_id < 0x4; ++thread_id) {
|
2014-07-22 21:10:37 -07:00
|
|
|
InterruptRelayQueue* interrupt_relay_queue = GetInterruptRelayQueue(thread_id);
|
|
|
|
u8 next = interrupt_relay_queue->index;
|
|
|
|
next += interrupt_relay_queue->number_interrupts;
|
|
|
|
next = next % 0x34; // 0x34 is the number of interrupt slots
|
|
|
|
|
2015-01-13 21:26:27 -08:00
|
|
|
interrupt_relay_queue->number_interrupts += 1;
|
|
|
|
|
2014-07-22 21:10:37 -07:00
|
|
|
interrupt_relay_queue->slot[next] = interrupt_id;
|
|
|
|
interrupt_relay_queue->error_code = 0x0; // No error
|
2015-01-13 17:55:56 -08:00
|
|
|
|
|
|
|
// Update framebuffer information if requested
|
|
|
|
// TODO(yuriks): Confirm where this code should be called. It is definitely updated without
|
|
|
|
// executing any GSP commands, only waiting on the event.
|
2015-02-10 16:57:48 -08:00
|
|
|
int screen_id = (interrupt_id == InterruptId::PDC0) ? 0 : (interrupt_id == InterruptId::PDC1) ? 1 : -1;
|
2015-02-09 19:45:54 -08:00
|
|
|
if (screen_id != -1) {
|
2015-01-13 17:55:56 -08:00
|
|
|
FrameBufferUpdate* info = GetFrameBufferInfo(thread_id, screen_id);
|
|
|
|
if (info->is_dirty) {
|
|
|
|
SetBufferSwap(screen_id, info->framebuffer_info[info->index]);
|
2015-02-09 19:45:54 -08:00
|
|
|
info->is_dirty = false;
|
2015-01-13 17:55:56 -08:00
|
|
|
}
|
|
|
|
}
|
2014-07-22 19:59:26 -07:00
|
|
|
}
|
2015-01-22 21:11:25 -08:00
|
|
|
g_interrupt_event->Signal();
|
2014-07-22 19:59:26 -07:00
|
|
|
}
|
2014-05-17 13:26:45 -07:00
|
|
|
|
2014-07-22 19:59:26 -07:00
|
|
|
/// Executes the next GSP command
|
2014-11-16 19:58:39 -08:00
|
|
|
static void ExecuteCommand(const Command& command, u32 thread_id) {
|
2014-07-16 02:24:09 -07:00
|
|
|
// Utility function to convert register ID to address
|
|
|
|
auto WriteGPURegister = [](u32 id, u32 data) {
|
|
|
|
GPU::Write<u32>(0x1EF00000 + 4 * id, data);
|
|
|
|
};
|
|
|
|
|
2014-07-22 03:41:16 -07:00
|
|
|
switch (command.id) {
|
2014-05-07 18:04:55 -07:00
|
|
|
|
|
|
|
// GX request DMA - typically used for copying memory from GSP heap to VRAM
|
2014-07-22 20:26:28 -07:00
|
|
|
case CommandId::REQUEST_DMA:
|
2014-07-22 03:41:16 -07:00
|
|
|
memcpy(Memory::GetPointer(command.dma_request.dest_address),
|
|
|
|
Memory::GetPointer(command.dma_request.source_address),
|
|
|
|
command.dma_request.size);
|
2014-12-02 22:04:22 -08:00
|
|
|
SignalInterrupt(InterruptId::DMA);
|
2014-05-07 18:04:55 -07:00
|
|
|
break;
|
|
|
|
|
2014-07-22 04:04:16 -07:00
|
|
|
// ctrulib homebrew sends all relevant command list data with this command,
|
|
|
|
// hence we do all "interesting" stuff here and do nothing in SET_COMMAND_LIST_FIRST.
|
|
|
|
// TODO: This will need some rework in the future.
|
2014-07-22 20:26:28 -07:00
|
|
|
case CommandId::SET_COMMAND_LIST_LAST:
|
2014-07-22 03:41:16 -07:00
|
|
|
{
|
|
|
|
auto& params = command.set_command_list_last;
|
2014-12-02 22:04:22 -08:00
|
|
|
|
2015-02-01 12:31:21 -08:00
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.address)),
|
|
|
|
Memory::VirtualToPhysicalAddress(params.address) >> 3);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.size)), params.size);
|
2014-07-22 21:10:37 -07:00
|
|
|
|
|
|
|
// TODO: Not sure if we are supposed to always write this .. seems to trigger processing though
|
2015-02-01 12:31:21 -08:00
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(command_processor_config.trigger)), 1);
|
2014-05-18 08:28:30 -07:00
|
|
|
|
2014-05-17 13:26:45 -07:00
|
|
|
break;
|
2014-07-22 03:41:16 -07:00
|
|
|
}
|
2014-05-17 13:26:45 -07:00
|
|
|
|
2014-07-22 04:04:16 -07:00
|
|
|
// It's assumed that the two "blocks" behave equivalently.
|
|
|
|
// Presumably this is done simply to allow two memory fills to run in parallel.
|
2014-07-22 20:26:28 -07:00
|
|
|
case CommandId::SET_MEMORY_FILL:
|
2014-07-22 03:41:16 -07:00
|
|
|
{
|
|
|
|
auto& params = command.memory_fill;
|
2015-01-01 10:58:18 -08:00
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_start)),
|
|
|
|
Memory::VirtualToPhysicalAddress(params.start1) >> 3);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].address_end)),
|
|
|
|
Memory::VirtualToPhysicalAddress(params.end1) >> 3);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].value_32bit)), params.value1);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[0].control)), params.control1);
|
|
|
|
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_start)),
|
|
|
|
Memory::VirtualToPhysicalAddress(params.start2) >> 3);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].address_end)),
|
|
|
|
Memory::VirtualToPhysicalAddress(params.end2) >> 3);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].value_32bit)), params.value2);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(memory_fill_config[1].control)), params.control2);
|
2014-05-17 13:26:45 -07:00
|
|
|
break;
|
2014-07-22 03:41:16 -07:00
|
|
|
}
|
2014-05-17 13:26:45 -07:00
|
|
|
|
2014-07-22 20:26:28 -07:00
|
|
|
case CommandId::SET_DISPLAY_TRANSFER:
|
2014-07-23 05:42:15 -07:00
|
|
|
{
|
|
|
|
auto& params = command.image_copy;
|
2015-01-01 10:58:18 -08:00
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
|
2015-02-01 12:31:21 -08:00
|
|
|
Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
|
2015-01-01 10:58:18 -08:00
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
|
2015-02-01 12:31:21 -08:00
|
|
|
Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.flags)), params.flags);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.trigger)), 1);
|
2014-07-22 19:59:26 -07:00
|
|
|
break;
|
2014-07-23 05:42:15 -07:00
|
|
|
}
|
2014-07-22 19:59:26 -07:00
|
|
|
|
2014-07-23 05:42:15 -07:00
|
|
|
// TODO: Check if texture copies are implemented correctly..
|
2014-07-22 20:26:28 -07:00
|
|
|
case CommandId::SET_TEXTURE_COPY:
|
2014-07-22 03:41:16 -07:00
|
|
|
{
|
|
|
|
auto& params = command.image_copy;
|
2015-01-01 10:58:18 -08:00
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_address)),
|
2015-02-01 12:31:21 -08:00
|
|
|
Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
|
2015-01-01 10:58:18 -08:00
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_address)),
|
2015-02-01 12:31:21 -08:00
|
|
|
Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.input_size)), params.in_buffer_size);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.output_size)), params.out_buffer_size);
|
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.flags)), params.flags);
|
2014-07-16 02:24:09 -07:00
|
|
|
|
2014-07-23 05:42:15 -07:00
|
|
|
// TODO: Should this register be set to 1 or should instead its value be OR-ed with 1?
|
2015-02-01 12:31:21 -08:00
|
|
|
WriteGPURegister(static_cast<u32>(GPU_REG_INDEX(display_transfer_config.trigger)), 1);
|
2014-05-17 13:26:45 -07:00
|
|
|
break;
|
2014-07-22 03:41:16 -07:00
|
|
|
}
|
2014-05-17 13:26:45 -07:00
|
|
|
|
2014-07-22 04:04:16 -07:00
|
|
|
// TODO: Figure out what exactly SET_COMMAND_LIST_FIRST and SET_COMMAND_LIST_LAST
|
|
|
|
// are supposed to do.
|
2014-07-22 20:26:28 -07:00
|
|
|
case CommandId::SET_COMMAND_LIST_FIRST:
|
2014-05-17 13:26:45 -07:00
|
|
|
{
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-05-07 18:04:55 -07:00
|
|
|
default:
|
2014-12-05 17:53:49 -08:00
|
|
|
LOG_ERROR(Service_GSP, "unknown command 0x%08X", (int)command.id.Value());
|
2014-05-07 18:04:55 -07:00
|
|
|
}
|
2014-07-22 19:59:26 -07:00
|
|
|
}
|
2014-05-17 13:26:45 -07:00
|
|
|
|
2015-03-05 19:38:23 -08:00
|
|
|
/**
|
|
|
|
* GSP_GPU::SetLcdForceBlack service function
|
|
|
|
*
|
|
|
|
* Enable or disable REG_LCDCOLORFILL with the color black.
|
|
|
|
*
|
|
|
|
* Inputs:
|
|
|
|
* 1: Black color fill flag (0 = don't fill, !0 = fill)
|
|
|
|
* Outputs:
|
|
|
|
* 1: Result code
|
|
|
|
*/
|
2014-10-12 22:40:26 -07:00
|
|
|
static void SetLcdForceBlack(Service::Interface* self) {
|
2015-03-05 19:38:23 -08:00
|
|
|
u32* cmd_buff = Kernel::GetCommandBuffer();
|
2014-10-12 22:40:26 -07:00
|
|
|
|
2015-03-05 19:38:23 -08:00
|
|
|
bool enable_black = cmd_buff[1] != 0;
|
2014-10-12 22:40:26 -07:00
|
|
|
LCD::Regs::ColorFill data = {0};
|
2015-03-05 19:38:23 -08:00
|
|
|
|
2014-10-12 22:40:26 -07:00
|
|
|
// Since data is already zeroed, there is no need to explicitly set
|
|
|
|
// the color to black (all zero).
|
|
|
|
data.is_enabled = enable_black;
|
2015-03-05 19:38:23 -08:00
|
|
|
|
2014-10-12 22:40:26 -07:00
|
|
|
LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_top), data.raw); // Top LCD
|
|
|
|
LCD::Write(HW::VADDR_LCD + 4 * LCD_REG_INDEX(color_fill_bottom), data.raw); // Bottom LCD
|
2015-03-05 19:38:23 -08:00
|
|
|
|
|
|
|
cmd_buff[1] = RESULT_SUCCESS.raw;
|
|
|
|
}
|
|
|
|
|
2014-07-22 19:59:26 -07:00
|
|
|
/// This triggers handling of the GX command written to the command buffer in shared memory.
|
2014-11-16 19:58:39 -08:00
|
|
|
static void TriggerCmdReqQueue(Service::Interface* self) {
|
2014-07-22 19:59:26 -07:00
|
|
|
// Iterate through each thread's command queue...
|
2014-07-22 21:10:37 -07:00
|
|
|
for (unsigned thread_id = 0; thread_id < 0x4; ++thread_id) {
|
|
|
|
CommandBuffer* command_buffer = (CommandBuffer*)GetCommandBuffer(thread_id);
|
2014-07-22 19:59:26 -07:00
|
|
|
|
|
|
|
// Iterate through each command...
|
2014-07-22 21:10:37 -07:00
|
|
|
for (unsigned i = 0; i < command_buffer->number_commands; ++i) {
|
|
|
|
g_debugger.GXCommandProcessed((u8*)&command_buffer->commands[i]);
|
|
|
|
|
|
|
|
// Decode and execute command
|
2014-08-19 11:57:43 -07:00
|
|
|
ExecuteCommand(command_buffer->commands[i], thread_id);
|
2014-07-22 21:10:37 -07:00
|
|
|
|
|
|
|
// Indicates that command has completed
|
|
|
|
command_buffer->number_commands = command_buffer->number_commands - 1;
|
2014-07-22 19:59:26 -07:00
|
|
|
}
|
|
|
|
}
|
2014-12-09 15:43:42 -08:00
|
|
|
|
2014-12-13 21:30:11 -08:00
|
|
|
u32* cmd_buff = Kernel::GetCommandBuffer();
|
2014-12-09 15:43:42 -08:00
|
|
|
cmd_buff[1] = 0; // No error
|
2014-04-24 19:20:13 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
const Interface::FunctionInfo FunctionTable[] = {
|
2014-06-01 04:58:14 -07:00
|
|
|
{0x00010082, WriteHWRegs, "WriteHWRegs"},
|
2015-02-10 18:07:59 -08:00
|
|
|
{0x00020084, WriteHWRegsWithMask, "WriteHWRegsWithMask"},
|
2014-06-05 21:35:49 -07:00
|
|
|
{0x00030082, nullptr, "WriteHWRegRepeat"},
|
2014-04-25 22:48:24 -07:00
|
|
|
{0x00040080, ReadHWRegs, "ReadHWRegs"},
|
2014-07-25 02:23:28 -07:00
|
|
|
{0x00050200, SetBufferSwap, "SetBufferSwap"},
|
2014-06-05 21:35:49 -07:00
|
|
|
{0x00060082, nullptr, "SetCommandList"},
|
|
|
|
{0x000700C2, nullptr, "RequestDma"},
|
2014-12-17 21:35:12 -08:00
|
|
|
{0x00080082, FlushDataCache, "FlushDataCache"},
|
2014-06-05 21:35:49 -07:00
|
|
|
{0x00090082, nullptr, "InvalidateDataCache"},
|
|
|
|
{0x000A0044, nullptr, "RegisterInterruptEvents"},
|
2015-03-05 19:38:23 -08:00
|
|
|
{0x000B0040, SetLcdForceBlack, "SetLcdForceBlack"},
|
2014-05-07 18:04:55 -07:00
|
|
|
{0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"},
|
2014-06-05 21:35:49 -07:00
|
|
|
{0x000D0140, nullptr, "SetDisplayTransfer"},
|
|
|
|
{0x000E0180, nullptr, "SetTextureCopy"},
|
|
|
|
{0x000F0200, nullptr, "SetMemoryFill"},
|
|
|
|
{0x00100040, nullptr, "SetAxiConfigQoSMode"},
|
|
|
|
{0x00110040, nullptr, "SetPerfLogMode"},
|
|
|
|
{0x00120000, nullptr, "GetPerfLog"},
|
2014-04-24 19:20:13 -07:00
|
|
|
{0x00130042, RegisterInterruptRelayQueue, "RegisterInterruptRelayQueue"},
|
2014-06-05 21:35:49 -07:00
|
|
|
{0x00140000, nullptr, "UnregisterInterruptRelayQueue"},
|
|
|
|
{0x00150002, nullptr, "TryAcquireRight"},
|
|
|
|
{0x00160042, nullptr, "AcquireRight"},
|
|
|
|
{0x00170000, nullptr, "ReleaseRight"},
|
|
|
|
{0x00180000, nullptr, "ImportDisplayCaptureInfo"},
|
|
|
|
{0x00190000, nullptr, "SaveVramSysArea"},
|
|
|
|
{0x001A0000, nullptr, "RestoreVramSysArea"},
|
|
|
|
{0x001B0000, nullptr, "ResetGpuCore"},
|
|
|
|
{0x001C0040, nullptr, "SetLedForceOff"},
|
|
|
|
{0x001D0040, nullptr, "SetTestCommand"},
|
|
|
|
{0x001E0080, nullptr, "SetInternalPriorities"},
|
2014-09-30 09:13:29 -07:00
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|
|
{0x001F0082, nullptr, "StoreDataCache"},
|
2014-04-15 21:03:41 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////////////////////////
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|
|
|
// Interface class
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|
|
|
|
|
|
|
Interface::Interface() {
|
2015-01-30 10:56:49 -08:00
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|
|
Register(FunctionTable);
|
2014-07-22 20:36:50 -07:00
|
|
|
|
2014-07-22 21:10:37 -07:00
|
|
|
g_interrupt_event = 0;
|
2015-05-10 15:51:37 -07:00
|
|
|
|
|
|
|
using Kernel::MemoryPermission;
|
|
|
|
g_shared_memory = Kernel::SharedMemory::Create(0x1000, MemoryPermission::ReadWrite,
|
|
|
|
MemoryPermission::ReadWrite, "GSPSharedMem");
|
|
|
|
|
|
|
|
g_thread_id = 0;
|
2014-04-15 21:03:41 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
} // namespace
|