2018-03-19 16:00:29 -07:00
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// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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2018-04-15 17:52:25 -07:00
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#include "common/assert.h"
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2018-03-19 16:00:29 -07:00
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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namespace Texture {
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enum class TextureFormat : u32 {
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A8R8G8B8 = 0x8,
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A2B10G10R10 = 0x9,
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2018-05-27 07:02:05 -07:00
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A1B5G5R5 = 0x14,
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B5G6R5 = 0x15,
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DXT1 = 0x24,
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DXT23 = 0x25,
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DXT45 = 0x26,
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};
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2018-03-26 13:44:20 -07:00
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enum class TextureType : u32 {
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Texture1D = 0,
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Texture2D = 1,
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Texture3D = 2,
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TextureCubemap = 3,
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Texture1DArray = 4,
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Texture2DArray = 5,
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Texture1DBuffer = 6,
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Texture2DNoMipmap = 7,
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TextureCubeArray = 8,
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};
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enum class TICHeaderVersion : u32 {
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OneDBuffer = 0,
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PitchColorKey = 1,
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Pitch = 2,
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BlockLinear = 3,
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BlockLinearColorKey = 4,
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};
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2018-03-29 11:12:53 -07:00
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enum class ComponentType : u32 {
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SNORM = 1,
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UNORM = 2,
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SINT = 3,
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UINT = 4,
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SNORM_FORCE_FP16 = 5,
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UNORM_FORCE_FP16 = 6,
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FLOAT = 7
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};
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union TextureHandle {
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u32 raw;
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BitField<0, 20, u32> tic_id;
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BitField<20, 12, u32> tsc_id;
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};
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static_assert(sizeof(TextureHandle) == 4, "TextureHandle has wrong size");
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struct TICEntry {
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static constexpr u32 DefaultBlockHeight = 16;
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union {
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u32 raw;
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BitField<0, 7, TextureFormat> format;
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BitField<7, 3, ComponentType> r_type;
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BitField<10, 3, ComponentType> g_type;
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BitField<13, 3, ComponentType> b_type;
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BitField<16, 3, ComponentType> a_type;
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};
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u32 address_low;
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union {
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BitField<0, 16, u32> address_high;
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BitField<21, 3, TICHeaderVersion> header_version;
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};
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union {
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BitField<3, 3, u32> block_height;
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// High 16 bits of the pitch value
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BitField<0, 16, u32> pitch_high;
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};
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union {
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BitField<0, 16, u32> width_minus_1;
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BitField<23, 4, TextureType> texture_type;
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};
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u16 height_minus_1;
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INSERT_PADDING_BYTES(10);
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | address_low);
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}
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u32 Pitch() const {
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ASSERT(header_version == TICHeaderVersion::Pitch ||
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header_version == TICHeaderVersion::PitchColorKey);
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// The pitch value is 21 bits, and is 32B aligned.
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return pitch_high << 5;
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}
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u32 Width() const {
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return width_minus_1 + 1;
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}
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u32 Height() const {
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return height_minus_1 + 1;
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}
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2018-03-26 19:40:30 -07:00
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u32 BlockHeight() const {
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ASSERT(header_version == TICHeaderVersion::BlockLinear ||
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header_version == TICHeaderVersion::BlockLinearColorKey);
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// The block height is stored in log2 format.
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return 1 << block_height;
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}
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2018-03-26 19:40:30 -07:00
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bool IsTiled() const {
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return header_version == TICHeaderVersion::BlockLinear ||
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header_version == TICHeaderVersion::BlockLinearColorKey;
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}
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};
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static_assert(sizeof(TICEntry) == 0x20, "TICEntry has wrong size");
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2018-03-26 13:45:05 -07:00
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enum class WrapMode : u32 {
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Wrap = 0,
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Mirror = 1,
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ClampToEdge = 2,
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Border = 3,
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ClampOGL = 4,
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MirrorOnceClampToEdge = 5,
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MirrorOnceBorder = 6,
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MirrorOnceClampOGL = 7,
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};
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enum class TextureFilter : u32 {
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Nearest = 1,
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Linear = 2,
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};
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enum class TextureMipmapFilter : u32 {
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None = 1,
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Nearest = 2,
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Linear = 3,
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};
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struct TSCEntry {
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union {
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BitField<0, 3, WrapMode> wrap_u;
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BitField<3, 3, WrapMode> wrap_v;
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BitField<6, 3, WrapMode> wrap_p;
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BitField<9, 1, u32> depth_compare_enabled;
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BitField<10, 3, u32> depth_compare_func;
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};
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union {
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BitField<0, 2, TextureFilter> mag_filter;
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BitField<4, 2, TextureFilter> min_filter;
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BitField<6, 2, TextureMipmapFilter> mip_filter;
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};
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INSERT_PADDING_BYTES(8);
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u32 border_color_r;
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u32 border_color_g;
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u32 border_color_b;
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u32 border_color_a;
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};
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static_assert(sizeof(TSCEntry) == 0x20, "TSCEntry has wrong size");
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struct FullTextureInfo {
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u32 index;
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TICEntry tic;
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TSCEntry tsc;
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bool enabled;
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};
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2018-03-22 13:17:10 -07:00
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/// Returns the number of bytes per pixel of the input texture format.
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u32 BytesPerPixel(TextureFormat format);
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2018-03-19 16:00:29 -07:00
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} // namespace Texture
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} // namespace Tegra
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