2018-02-11 18:34:20 -08:00
|
|
|
// Copyright 2018 yuzu Emulator Project
|
|
|
|
// Licensed under GPLv2 or any later version
|
|
|
|
// Refer to the license.txt file included.
|
|
|
|
|
2019-03-05 17:25:01 -08:00
|
|
|
#include "common/assert.h"
|
|
|
|
#include "common/logging/log.h"
|
2018-02-11 18:34:20 -08:00
|
|
|
#include "video_core/engines/fermi_2d.h"
|
2019-04-05 15:21:15 -07:00
|
|
|
#include "video_core/memory_manager.h"
|
2018-10-05 20:46:40 -07:00
|
|
|
#include "video_core/rasterizer_interface.h"
|
2018-02-11 18:34:20 -08:00
|
|
|
|
2018-07-20 15:14:17 -07:00
|
|
|
namespace Tegra::Engines {
|
2018-02-11 18:34:20 -08:00
|
|
|
|
2019-08-30 11:08:00 -07:00
|
|
|
Fermi2D::Fermi2D(VideoCore::RasterizerInterface& rasterizer) : rasterizer{rasterizer} {}
|
2018-04-23 18:12:40 -07:00
|
|
|
|
2018-11-23 20:20:56 -08:00
|
|
|
void Fermi2D::CallMethod(const GPU::MethodCall& method_call) {
|
|
|
|
ASSERT_MSG(method_call.method < Regs::NUM_REGS,
|
2018-04-23 18:12:40 -07:00
|
|
|
"Invalid Fermi2D register, increase the size of the Regs structure");
|
2018-04-24 20:00:40 -07:00
|
|
|
|
2018-11-23 20:20:56 -08:00
|
|
|
regs.reg_array[method_call.method] = method_call.argument;
|
2018-04-24 20:00:40 -07:00
|
|
|
|
2018-11-23 20:20:56 -08:00
|
|
|
switch (method_call.method) {
|
2018-12-14 21:20:00 -08:00
|
|
|
// Trigger the surface copy on the last register write. This is blit_src_y, but this is 64-bit,
|
|
|
|
// so trigger on the second 32-bit write.
|
|
|
|
case FERMI2D_REG_INDEX(blit_src_y) + 1: {
|
2018-04-24 20:00:40 -07:00
|
|
|
HandleSurfaceCopy();
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-10-17 15:21:01 -07:00
|
|
|
std::pair<u32, u32> DelimitLine(u32 src_1, u32 src_2, u32 dst_1, u32 dst_2, u32 src_line) {
|
|
|
|
const u32 line_a = src_2 - src_1;
|
|
|
|
const u32 line_b = dst_2 - dst_1;
|
|
|
|
const u32 excess = std::max<s32>(0, line_a - src_line + src_1);
|
|
|
|
return {line_b - (excess * line_b) / line_a, excess};
|
|
|
|
}
|
|
|
|
|
2018-04-24 20:00:40 -07:00
|
|
|
void Fermi2D::HandleSurfaceCopy() {
|
2019-09-21 17:18:57 -07:00
|
|
|
LOG_DEBUG(HW_GPU, "Requested a surface copy with operation {}",
|
2019-09-21 17:21:56 -07:00
|
|
|
static_cast<u32>(regs.operation));
|
2018-04-24 20:00:40 -07:00
|
|
|
|
|
|
|
// TODO(Subv): Only raw copies are implemented.
|
2019-05-18 01:57:49 -07:00
|
|
|
ASSERT(regs.operation == Operation::SrcCopy);
|
2018-04-24 20:00:40 -07:00
|
|
|
|
2018-12-14 21:20:00 -08:00
|
|
|
const u32 src_blit_x1{static_cast<u32>(regs.blit_src_x >> 32)};
|
|
|
|
const u32 src_blit_y1{static_cast<u32>(regs.blit_src_y >> 32)};
|
2019-06-12 13:20:20 -07:00
|
|
|
u32 src_blit_x2, src_blit_y2;
|
|
|
|
if (regs.blit_control.origin == Origin::Corner) {
|
|
|
|
src_blit_x2 =
|
|
|
|
static_cast<u32>((regs.blit_src_x + (regs.blit_du_dx * regs.blit_dst_width)) >> 32);
|
|
|
|
src_blit_y2 =
|
|
|
|
static_cast<u32>((regs.blit_src_y + (regs.blit_dv_dy * regs.blit_dst_height)) >> 32);
|
|
|
|
} else {
|
|
|
|
src_blit_x2 = static_cast<u32>((regs.blit_src_x >> 32) + regs.blit_dst_width);
|
|
|
|
src_blit_y2 = static_cast<u32>((regs.blit_src_y >> 32) + regs.blit_dst_height);
|
|
|
|
}
|
2019-10-17 15:21:01 -07:00
|
|
|
u32 dst_blit_x2 = regs.blit_dst_x + regs.blit_dst_width;
|
|
|
|
u32 dst_blit_y2 = regs.blit_dst_y + regs.blit_dst_height;
|
|
|
|
const auto [new_dst_w, src_excess_x] =
|
|
|
|
DelimitLine(src_blit_x1, src_blit_x2, regs.blit_dst_x, dst_blit_x2, regs.src.width);
|
|
|
|
const auto [new_dst_h, src_excess_y] =
|
|
|
|
DelimitLine(src_blit_y1, src_blit_y2, regs.blit_dst_y, dst_blit_y2, regs.src.height);
|
|
|
|
dst_blit_x2 = new_dst_w + regs.blit_dst_x;
|
|
|
|
src_blit_x2 = src_blit_x2 - src_excess_x;
|
|
|
|
dst_blit_y2 = new_dst_h + regs.blit_dst_y;
|
|
|
|
src_blit_y2 = src_blit_y2 - src_excess_y;
|
|
|
|
const auto [new_src_w, dst_excess_x] =
|
|
|
|
DelimitLine(regs.blit_dst_x, dst_blit_x2, src_blit_x1, src_blit_x2, regs.dst.width);
|
|
|
|
const auto [new_src_h, dst_excess_y] =
|
|
|
|
DelimitLine(regs.blit_dst_y, dst_blit_y2, src_blit_y1, src_blit_y2, regs.dst.height);
|
|
|
|
src_blit_x2 = new_src_w + src_blit_x1;
|
|
|
|
dst_blit_x2 = dst_blit_x2 - dst_excess_x;
|
|
|
|
src_blit_y2 = new_src_h + src_blit_y1;
|
|
|
|
dst_blit_y2 = dst_blit_y2 - dst_excess_y;
|
|
|
|
const Common::Rectangle<u32> src_rect{src_blit_x1, src_blit_y1, src_blit_x2, src_blit_y2};
|
|
|
|
const Common::Rectangle<u32> dst_rect{regs.blit_dst_x, regs.blit_dst_y, dst_blit_x2,
|
|
|
|
dst_blit_y2};
|
2019-05-18 01:57:49 -07:00
|
|
|
Config copy_config;
|
|
|
|
copy_config.operation = regs.operation;
|
|
|
|
copy_config.filter = regs.blit_control.filter;
|
|
|
|
copy_config.src_rect = src_rect;
|
|
|
|
copy_config.dst_rect = dst_rect;
|
2018-10-05 20:46:40 -07:00
|
|
|
|
2019-05-18 01:57:49 -07:00
|
|
|
if (!rasterizer.AccelerateSurfaceCopy(regs.src, regs.dst, copy_config)) {
|
2018-12-14 21:20:00 -08:00
|
|
|
UNIMPLEMENTED();
|
2018-04-24 20:00:40 -07:00
|
|
|
}
|
2018-04-23 18:12:40 -07:00
|
|
|
}
|
2018-02-11 18:34:20 -08:00
|
|
|
|
2018-07-20 15:14:17 -07:00
|
|
|
} // namespace Tegra::Engines
|