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https://github.com/starr-dusT/yuzu-mainline
synced 2024-03-05 21:12:25 -08:00
gl_rasterizer_cache: Use GPU PAGE_BITS/SIZE, not CPU.
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@ -1428,9 +1428,9 @@ void RasterizerCacheOpenGL::UnregisterSurface(const Surface& surface) {
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}
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}
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void RasterizerCacheOpenGL::UpdatePagesCachedCount(Tegra::GPUVAddr addr, u64 size, int delta) {
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void RasterizerCacheOpenGL::UpdatePagesCachedCount(Tegra::GPUVAddr addr, u64 size, int delta) {
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const u64 num_pages =
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const u64 num_pages = ((addr + size - 1) >> Tegra::MemoryManager::PAGE_BITS) -
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((addr + size - 1) >> Memory::PAGE_BITS) - (addr >> Memory::PAGE_BITS) + 1;
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(addr >> Tegra::MemoryManager::PAGE_BITS) + 1;
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const u64 page_start = addr >> Memory::PAGE_BITS;
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const u64 page_start = addr >> Tegra::MemoryManager::PAGE_BITS;
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const u64 page_end = page_start + num_pages;
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const u64 page_end = page_start + num_pages;
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// Interval maps will erase segments if count reaches 0, so if delta is negative we have to
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// Interval maps will erase segments if count reaches 0, so if delta is negative we have to
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@ -1444,9 +1444,9 @@ void RasterizerCacheOpenGL::UpdatePagesCachedCount(Tegra::GPUVAddr addr, u64 siz
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const int count = pair.second;
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const int count = pair.second;
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const Tegra::GPUVAddr interval_start_addr = boost::icl::first(interval)
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const Tegra::GPUVAddr interval_start_addr = boost::icl::first(interval)
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<< Memory::PAGE_BITS;
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<< Tegra::MemoryManager::PAGE_BITS;
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const Tegra::GPUVAddr interval_end_addr = boost::icl::last_next(interval)
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const Tegra::GPUVAddr interval_end_addr = boost::icl::last_next(interval)
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<< Memory::PAGE_BITS;
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<< Tegra::MemoryManager::PAGE_BITS;
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const u64 interval_size = interval_end_addr - interval_start_addr;
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const u64 interval_size = interval_end_addr - interval_start_addr;
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if (delta > 0 && count == delta)
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if (delta > 0 && count == delta)
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