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https://github.com/starr-dusT/yuzu-mainline
synced 2024-03-05 21:12:25 -08:00
shader_ir: propagate shader size to the IR
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8a6fc529a9
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@ -129,9 +129,11 @@ std::size_t CalculateProgramSize(const GLShader::ProgramCode& program) {
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/// Hashes one (or two) program streams
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u64 GetUniqueIdentifier(Maxwell::ShaderProgram program_type, const ProgramCode& code,
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const ProgramCode& code_b) {
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u64 unique_identifier =
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Common::CityHash64(reinterpret_cast<const char*>(code.data()), CalculateProgramSize(code));
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const ProgramCode& code_b, std::size_t size_a = 0, std::size_t size_b = 0) {
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if (size_a == 0) {
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size_a = CalculateProgramSize(code);
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}
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u64 unique_identifier = Common::CityHash64(reinterpret_cast<const char*>(code.data()), size_a);
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if (program_type != Maxwell::ShaderProgram::VertexA) {
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return unique_identifier;
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}
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@ -140,8 +142,11 @@ u64 GetUniqueIdentifier(Maxwell::ShaderProgram program_type, const ProgramCode&
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std::size_t seed = 0;
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boost::hash_combine(seed, unique_identifier);
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const u64 identifier_b = Common::CityHash64(reinterpret_cast<const char*>(code_b.data()),
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CalculateProgramSize(code_b));
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if (size_b == 0) {
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size_b = CalculateProgramSize(code_b);
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}
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const u64 identifier_b =
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Common::CityHash64(reinterpret_cast<const char*>(code_b.data()), size_b);
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boost::hash_combine(seed, identifier_b);
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return static_cast<u64>(seed);
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}
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@ -150,14 +155,17 @@ u64 GetUniqueIdentifier(Maxwell::ShaderProgram program_type, const ProgramCode&
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GLShader::ProgramResult CreateProgram(const Device& device, Maxwell::ShaderProgram program_type,
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ProgramCode program_code, ProgramCode program_code_b) {
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GLShader::ShaderSetup setup(program_code);
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setup.program.size_a = CalculateProgramSize(program_code);
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setup.program.size_b = 0;
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if (program_type == Maxwell::ShaderProgram::VertexA) {
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// VertexB is always enabled, so when VertexA is enabled, we have two vertex shaders.
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// Conventional HW does not support this, so we combine VertexA and VertexB into one
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// stage here.
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setup.SetProgramB(program_code_b);
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setup.program.size_b = CalculateProgramSize(program_code_b);
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}
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setup.program.unique_identifier =
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GetUniqueIdentifier(program_type, program_code, program_code_b);
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setup.program.unique_identifier = GetUniqueIdentifier(
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program_type, program_code, program_code_b, setup.program.size_a, setup.program.size_b);
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switch (program_type) {
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case Maxwell::ShaderProgram::VertexA:
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@ -29,14 +29,14 @@ layout (std140, binding = EMULATION_UBO_BINDING) uniform vs_config {
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};
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)";
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const ShaderIR program_ir(setup.program.code, PROGRAM_OFFSET);
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const ShaderIR program_ir(setup.program.code, PROGRAM_OFFSET, setup.program.size_a);
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ProgramResult program =
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Decompile(device, program_ir, Maxwell3D::Regs::ShaderStage::Vertex, "vertex");
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out += program.first;
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if (setup.IsDualProgram()) {
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const ShaderIR program_ir_b(setup.program.code_b, PROGRAM_OFFSET);
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const ShaderIR program_ir_b(setup.program.code_b, PROGRAM_OFFSET, setup.program.size_b);
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ProgramResult program_b =
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Decompile(device, program_ir_b, Maxwell3D::Regs::ShaderStage::Vertex, "vertex_b");
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@ -80,7 +80,7 @@ layout (std140, binding = EMULATION_UBO_BINDING) uniform gs_config {
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};
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)";
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const ShaderIR program_ir(setup.program.code, PROGRAM_OFFSET);
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const ShaderIR program_ir(setup.program.code, PROGRAM_OFFSET, setup.program.size_a);
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ProgramResult program =
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Decompile(device, program_ir, Maxwell3D::Regs::ShaderStage::Geometry, "geometry");
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out += program.first;
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@ -115,7 +115,7 @@ layout (std140, binding = EMULATION_UBO_BINDING) uniform fs_config {
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};
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)";
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const ShaderIR program_ir(setup.program.code, PROGRAM_OFFSET);
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const ShaderIR program_ir(setup.program.code, PROGRAM_OFFSET, setup.program.size_a);
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ProgramResult program =
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Decompile(device, program_ir, Maxwell3D::Regs::ShaderStage::Fragment, "fragment");
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@ -27,6 +27,8 @@ struct ShaderSetup {
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ProgramCode code;
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ProgramCode code_b; // Used for dual vertex shaders
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u64 unique_identifier;
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std::size_t size_a;
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std::size_t size_b;
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} program;
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/// Used in scenarios where we have a dual vertex shaders
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@ -39,7 +39,7 @@ void ShaderIR::Decode() {
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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ShaderCharacteristics shader_info{};
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bool can_proceed = ScanFlow(program_code, MAX_PROGRAM_LENGTH, main_offset, shader_info);
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bool can_proceed = ScanFlow(program_code, program_code.size(), main_offset, shader_info);
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if (can_proceed) {
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coverage_begin = shader_info.start;
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coverage_end = shader_info.end;
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@ -52,12 +52,12 @@ void ShaderIR::Decode() {
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}
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return;
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}
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LOG_CRITICAL(HW_GPU, "Flow Analysis failed, falling back to brute force compiling");
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LOG_WARNING(HW_GPU, "Flow Analysis failed, falling back to brute force compiling");
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// Now we need to deal with an undecompilable shader. We need to brute force
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// a shader that captures every position.
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coverage_begin = shader_info.start;
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const u32 shader_end = static_cast<u32>(MAX_PROGRAM_LENGTH);
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const u32 shader_end = static_cast<u32>(program_size / sizeof(u64));
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coverage_end = shader_end;
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for (u32 label = main_offset; label < shader_end; label++) {
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basic_blocks.insert({label, DecodeRange(label, label + 1)});
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@ -22,8 +22,8 @@ using Tegra::Shader::PredCondition;
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using Tegra::Shader::PredOperation;
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using Tegra::Shader::Register;
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ShaderIR::ShaderIR(const ProgramCode& program_code, u32 main_offset)
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: program_code{program_code}, main_offset{main_offset} {
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ShaderIR::ShaderIR(const ProgramCode& program_code, u32 main_offset, const std::size_t size)
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: program_code{program_code}, main_offset{main_offset}, program_size{size} {
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Decode();
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}
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@ -65,7 +65,7 @@ struct GlobalMemoryUsage {
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class ShaderIR final {
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public:
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explicit ShaderIR(const ProgramCode& program_code, u32 main_offset);
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explicit ShaderIR(const ProgramCode& program_code, u32 main_offset, std::size_t size);
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~ShaderIR();
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const std::map<u32, NodeBlock>& GetBasicBlocks() const {
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@ -316,6 +316,7 @@ private:
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const ProgramCode& program_code;
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const u32 main_offset;
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const std::size_t program_size;
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u32 coverage_begin{};
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u32 coverage_end{};
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