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https://github.com/starr-dusT/yuzu-mainline
synced 2024-03-05 21:12:25 -08:00
VideoCore/GPU: Delegate subchannel engines to the dma pusher.
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90e5694230
commit
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@ -27,6 +27,8 @@ void DmaPusher::DispatchCalls() {
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dma_pushbuffer_subindex = 0;
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dma_state.is_last_call = true;
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while (system.IsPoweredOn()) {
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if (!Step()) {
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break;
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@ -82,9 +84,11 @@ bool DmaPusher::Step() {
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index);
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CallMultiMethod(&command_header.argument, max_write);
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dma_state.method_count -= max_write;
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dma_state.is_last_call = true;
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index += max_write;
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continue;
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} else {
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dma_state.is_last_call = dma_state.method_count <= 1;
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CallMethod(command_header.argument);
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}
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@ -144,12 +148,22 @@ void DmaPusher::SetState(const CommandHeader& command_header) {
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}
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void DmaPusher::CallMethod(u32 argument) const {
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gpu.CallMethod({dma_state.method, argument, dma_state.subchannel, dma_state.method_count});
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if (dma_state.method < non_puller_methods) {
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gpu.CallMethod({dma_state.method, argument, dma_state.subchannel, dma_state.method_count});
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} else {
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subchannels[dma_state.subchannel]->CallMethod(dma_state.method, argument,
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dma_state.is_last_call);
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}
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}
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void DmaPusher::CallMultiMethod(const u32* base_start, u32 num_methods) const {
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gpu.CallMultiMethod(dma_state.method, dma_state.subchannel, base_start, num_methods,
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dma_state.method_count);
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if (dma_state.method < non_puller_methods) {
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gpu.CallMultiMethod(dma_state.method, dma_state.subchannel, base_start, num_methods,
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dma_state.method_count);
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} else {
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subchannels[dma_state.subchannel]->CallMultiMethod(dma_state.method, base_start,
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num_methods, dma_state.method_count);
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}
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}
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} // namespace Tegra
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@ -4,11 +4,13 @@
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#pragma once
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#include <array>
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#include <vector>
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#include <queue>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "video_core/engines/engine_interface.h"
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namespace Core {
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class System;
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@ -69,7 +71,13 @@ public:
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void DispatchCalls();
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void BindSubchannel(Tegra::Engines::EngineInterface* engine, u32 subchannel_id) {
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subchannels[subchannel_id] = engine;
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}
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private:
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static constexpr u32 non_puller_methods = 0x40;
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static constexpr u32 max_subchannels = 8;
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bool Step();
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void SetState(const CommandHeader& command_header);
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@ -88,6 +96,7 @@ private:
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u32 method_count; ///< Current method count
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u32 length_pending; ///< Large NI command length pending
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bool non_incrementing; ///< Current command's NI flag
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bool is_last_call;
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};
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DmaState dma_state{};
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@ -96,6 +105,8 @@ private:
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GPUVAddr dma_mget{}; ///< main pushbuffer last read address
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bool ib_enable{true}; ///< IB mode enabled
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std::array<Tegra::Engines::EngineInterface*, max_subchannels> subchannels{};
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GPU& gpu;
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Core::System& system;
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};
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@ -347,7 +347,27 @@ void GPU::ProcessBindMethod(const MethodCall& method_call) {
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// Bind the current subchannel to the desired engine id.
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LOG_DEBUG(HW_GPU, "Binding subchannel {} to engine {}", method_call.subchannel,
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method_call.argument);
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bound_engines[method_call.subchannel] = static_cast<EngineID>(method_call.argument);
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auto engine_id = static_cast<EngineID>(method_call.argument);
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bound_engines[method_call.subchannel] = static_cast<EngineID>(engine_id);
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switch (engine_id) {
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case EngineID::FERMI_TWOD_A:
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dma_pusher->BindSubchannel(fermi_2d.get(), method_call.subchannel);
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break;
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case EngineID::MAXWELL_B:
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dma_pusher->BindSubchannel(maxwell_3d.get(), method_call.subchannel);
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break;
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case EngineID::KEPLER_COMPUTE_B:
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dma_pusher->BindSubchannel(kepler_compute.get(), method_call.subchannel);
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break;
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case EngineID::MAXWELL_DMA_COPY_A:
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dma_pusher->BindSubchannel(maxwell_dma.get(), method_call.subchannel);
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break;
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case EngineID::KEPLER_INLINE_TO_MEMORY_B:
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dma_pusher->BindSubchannel(kepler_memory.get(), method_call.subchannel);
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented engine");
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}
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}
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void GPU::ProcessSemaphoreTriggerMethod() {
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