mirror of
https://github.com/starr-dusT/yuzu-mainline
synced 2024-03-05 21:12:25 -08:00
shader: Add subgroup masks
This commit is contained in:
parent
fc93bc2abd
commit
da6cf2632c
@ -390,8 +390,16 @@ void EmitContext::DefineInputs(const Info& info) {
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if (info.uses_local_invocation_id) {
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local_invocation_id = DefineInput(*this, U32[3], spv::BuiltIn::LocalInvocationId);
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}
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if (info.uses_subgroup_mask) {
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subgroup_mask_eq = DefineInput(*this, U32[4], spv::BuiltIn::SubgroupEqMaskKHR);
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subgroup_mask_lt = DefineInput(*this, U32[4], spv::BuiltIn::SubgroupLtMaskKHR);
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subgroup_mask_le = DefineInput(*this, U32[4], spv::BuiltIn::SubgroupLeMaskKHR);
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subgroup_mask_gt = DefineInput(*this, U32[4], spv::BuiltIn::SubgroupGtMaskKHR);
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subgroup_mask_ge = DefineInput(*this, U32[4], spv::BuiltIn::SubgroupGeMaskKHR);
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}
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if (info.uses_subgroup_invocation_id ||
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(profile.warp_size_potentially_larger_than_guest && info.uses_subgroup_vote)) {
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(profile.warp_size_potentially_larger_than_guest &&
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(info.uses_subgroup_vote || info.uses_subgroup_mask))) {
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subgroup_local_invocation_id =
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DefineInput(*this, U32[1], spv::BuiltIn::SubgroupLocalInvocationId);
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}
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@ -97,6 +97,11 @@ public:
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Id workgroup_id{};
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Id local_invocation_id{};
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Id subgroup_local_invocation_id{};
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Id subgroup_mask_eq{};
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Id subgroup_mask_lt{};
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Id subgroup_mask_le{};
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Id subgroup_mask_gt{};
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Id subgroup_mask_ge{};
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Id instance_id{};
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Id instance_index{};
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Id base_instance{};
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@ -401,6 +401,11 @@ Id EmitVoteAll(EmitContext& ctx, Id pred);
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Id EmitVoteAny(EmitContext& ctx, Id pred);
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Id EmitVoteEqual(EmitContext& ctx, Id pred);
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Id EmitSubgroupBallot(EmitContext& ctx, Id pred);
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Id EmitSubgroupEqMask(EmitContext& ctx);
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Id EmitSubgroupLtMask(EmitContext& ctx);
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Id EmitSubgroupLeMask(EmitContext& ctx);
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Id EmitSubgroupGtMask(EmitContext& ctx);
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Id EmitSubgroupGeMask(EmitContext& ctx);
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Id EmitShuffleIndex(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask);
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Id EmitShuffleUp(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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@ -6,10 +6,18 @@
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namespace Shader::Backend::SPIRV {
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namespace {
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Id LargeWarpBallot(EmitContext& ctx, Id ballot) {
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Id WarpExtract(EmitContext& ctx, Id value) {
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const Id shift{ctx.Constant(ctx.U32[1], 5)};
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const Id local_index{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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return ctx.OpVectorExtractDynamic(ctx.U32[1], ballot, local_index);
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return ctx.OpVectorExtractDynamic(ctx.U32[1], value, local_index);
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}
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Id LoadMask(EmitContext& ctx, Id mask) {
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const Id value{ctx.OpLoad(ctx.U32[4], mask)};
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpCompositeExtract(ctx.U32[1], value, 0U);
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}
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return WarpExtract(ctx, value);
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}
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void SetInBoundsFlag(IR::Inst* inst, Id result) {
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@ -47,8 +55,8 @@ Id EmitVoteAll(EmitContext& ctx, Id pred) {
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return ctx.OpSubgroupAllKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id active_mask{WarpExtract(ctx, mask_ballot)};
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const Id ballot{WarpExtract(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], ballot, active_mask)};
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return ctx.OpIEqual(ctx.U1, lhs, active_mask);
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}
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@ -58,8 +66,8 @@ Id EmitVoteAny(EmitContext& ctx, Id pred) {
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return ctx.OpSubgroupAnyKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id active_mask{WarpExtract(ctx, mask_ballot)};
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const Id ballot{WarpExtract(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], ballot, active_mask)};
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return ctx.OpINotEqual(ctx.U1, lhs, ctx.u32_zero_value);
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}
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@ -69,8 +77,8 @@ Id EmitVoteEqual(EmitContext& ctx, Id pred) {
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return ctx.OpSubgroupAllEqualKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id active_mask{WarpExtract(ctx, mask_ballot)};
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const Id ballot{WarpExtract(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseXor(ctx.U32[1], ballot, active_mask)};
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return ctx.OpLogicalOr(ctx.U1, ctx.OpIEqual(ctx.U1, lhs, ctx.u32_zero_value),
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ctx.OpIEqual(ctx.U1, lhs, active_mask));
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@ -81,7 +89,27 @@ Id EmitSubgroupBallot(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpCompositeExtract(ctx.U32[1], ballot, 0U);
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}
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return LargeWarpBallot(ctx, ballot);
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return WarpExtract(ctx, ballot);
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}
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Id EmitSubgroupEqMask(EmitContext& ctx) {
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return LoadMask(ctx, ctx.subgroup_mask_eq);
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}
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Id EmitSubgroupLtMask(EmitContext& ctx) {
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return LoadMask(ctx, ctx.subgroup_mask_lt);
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}
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Id EmitSubgroupLeMask(EmitContext& ctx) {
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return LoadMask(ctx, ctx.subgroup_mask_le);
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}
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Id EmitSubgroupGtMask(EmitContext& ctx) {
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return LoadMask(ctx, ctx.subgroup_mask_gt);
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}
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Id EmitSubgroupGeMask(EmitContext& ctx) {
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return LoadMask(ctx, ctx.subgroup_mask_ge);
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}
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Id EmitShuffleIndex(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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@ -1628,6 +1628,26 @@ U32 IREmitter::SubgroupBallot(const U1& value) {
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return Inst<U32>(Opcode::SubgroupBallot, value);
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}
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U32 IREmitter::SubgroupEqMask() {
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return Inst<U32>(Opcode::SubgroupEqMask);
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}
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U32 IREmitter::SubgroupLtMask() {
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return Inst<U32>(Opcode::SubgroupLtMask);
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}
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U32 IREmitter::SubgroupLeMask() {
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return Inst<U32>(Opcode::SubgroupLeMask);
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}
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U32 IREmitter::SubgroupGtMask() {
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return Inst<U32>(Opcode::SubgroupGtMask);
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}
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U32 IREmitter::SubgroupGeMask() {
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return Inst<U32>(Opcode::SubgroupGeMask);
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}
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U32 IREmitter::ShuffleIndex(const IR::U32& value, const IR::U32& index, const IR::U32& clamp,
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const IR::U32& seg_mask) {
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return Inst<U32>(Opcode::ShuffleIndex, value, index, clamp, seg_mask);
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@ -281,6 +281,11 @@ public:
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[[nodiscard]] U1 VoteAny(const U1& value);
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[[nodiscard]] U1 VoteEqual(const U1& value);
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[[nodiscard]] U32 SubgroupBallot(const U1& value);
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[[nodiscard]] U32 SubgroupEqMask();
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[[nodiscard]] U32 SubgroupLtMask();
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[[nodiscard]] U32 SubgroupLeMask();
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[[nodiscard]] U32 SubgroupGtMask();
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[[nodiscard]] U32 SubgroupGeMask();
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[[nodiscard]] U32 ShuffleIndex(const IR::U32& value, const IR::U32& index, const IR::U32& clamp,
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const IR::U32& seg_mask);
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[[nodiscard]] U32 ShuffleUp(const IR::U32& value, const IR::U32& index, const IR::U32& clamp,
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@ -417,6 +417,11 @@ OPCODE(VoteAll, U1, U1,
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OPCODE(VoteAny, U1, U1, )
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OPCODE(VoteEqual, U1, U1, )
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OPCODE(SubgroupBallot, U32, U1, )
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OPCODE(SubgroupEqMask, U32, )
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OPCODE(SubgroupLtMask, U32, )
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OPCODE(SubgroupLeMask, U32, )
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OPCODE(SubgroupGtMask, U32, )
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OPCODE(SubgroupGeMask, U32, )
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OPCODE(ShuffleIndex, U32, U32, U32, U32, U32, )
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OPCODE(ShuffleUp, U32, U32, U32, U32, U32, )
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OPCODE(ShuffleDown, U32, U32, U32, U32, U32, )
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@ -10,6 +10,7 @@ namespace Shader::Maxwell {
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namespace {
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enum class SpecialRegister : u64 {
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SR_LANEID = 0,
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SR_CLOCK = 1,
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SR_VIRTCFG = 2,
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SR_VIRTID = 3,
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SR_PM0 = 4,
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@ -20,6 +21,9 @@ enum class SpecialRegister : u64 {
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SR_PM5 = 9,
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SR_PM6 = 10,
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SR_PM7 = 11,
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SR12 = 12,
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SR13 = 13,
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SR14 = 14,
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SR_ORDERING_TICKET = 15,
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SR_PRIM_TYPE = 16,
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SR_INVOCATION_ID = 17,
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@ -41,44 +45,70 @@ enum class SpecialRegister : u64 {
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SR_TID_X = 33,
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SR_TID_Y = 34,
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SR_TID_Z = 35,
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SR_CTA_PARAM = 36,
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SR_CTAID_X = 37,
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SR_CTAID_Y = 38,
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SR_CTAID_Z = 39,
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SR_NTID = 49,
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SR_CirQueueIncrMinusOne = 50,
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SR_NLATC = 51,
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SR_SWINLO = 57,
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SR_SWINSZ = 58,
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SR_SMEMSZ = 59,
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SR_SMEMBANKS = 60,
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SR_LWINLO = 61,
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SR_LWINSZ = 62,
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SR_LMEMLOSZ = 63,
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SR_LMEMHIOFF = 64,
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SR_EQMASK = 65,
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SR_LTMASK = 66,
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SR_LEMASK = 67,
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SR_GTMASK = 68,
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SR_GEMASK = 69,
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SR_REGALLOC = 70,
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SR_GLOBALERRORSTATUS = 73,
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SR_WARPERRORSTATUS = 75,
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SR_PM_HI0 = 81,
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SR_PM_HI1 = 82,
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SR_PM_HI2 = 83,
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SR_PM_HI3 = 84,
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SR_PM_HI4 = 85,
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SR_PM_HI5 = 86,
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SR_PM_HI6 = 87,
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SR_PM_HI7 = 88,
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SR_CLOCKLO = 89,
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SR_CLOCKHI = 90,
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SR_GLOBALTIMERLO = 91,
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SR_GLOBALTIMERHI = 92,
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SR_HWTASKID = 105,
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SR_CIRCULARQUEUEENTRYINDEX = 106,
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SR_CIRCULARQUEUEENTRYADDRESSLOW = 107,
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SR_CIRCULARQUEUEENTRYADDRESSHIGH = 108,
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SR_NTID = 40,
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SR_CirQueueIncrMinusOne = 41,
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SR_NLATC = 42,
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SR43 = 43,
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SR_SM_SPA_VERSION = 44,
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SR_MULTIPASSSHADERINFO = 45,
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SR_LWINHI = 46,
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SR_SWINHI = 47,
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SR_SWINLO = 48,
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SR_SWINSZ = 49,
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SR_SMEMSZ = 50,
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SR_SMEMBANKS = 51,
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SR_LWINLO = 52,
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SR_LWINSZ = 53,
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SR_LMEMLOSZ = 54,
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SR_LMEMHIOFF = 55,
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SR_EQMASK = 56,
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SR_LTMASK = 57,
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SR_LEMASK = 58,
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SR_GTMASK = 59,
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SR_GEMASK = 60,
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SR_REGALLOC = 61,
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SR_BARRIERALLOC = 62,
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SR63 = 63,
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SR_GLOBALERRORSTATUS = 64,
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SR65 = 65,
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SR_WARPERRORSTATUS = 66,
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SR_WARPERRORSTATUSCLEAR = 67,
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SR68 = 68,
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SR69 = 69,
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SR70 = 70,
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SR71 = 71,
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SR_PM_HI0 = 72,
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SR_PM_HI1 = 73,
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SR_PM_HI2 = 74,
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SR_PM_HI3 = 75,
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SR_PM_HI4 = 76,
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SR_PM_HI5 = 77,
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SR_PM_HI6 = 78,
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SR_PM_HI7 = 79,
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SR_CLOCKLO = 80,
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SR_CLOCKHI = 81,
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SR_GLOBALTIMERLO = 82,
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SR_GLOBALTIMERHI = 83,
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SR84 = 84,
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SR85 = 85,
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SR86 = 86,
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SR87 = 87,
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SR88 = 88,
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SR89 = 89,
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SR90 = 90,
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SR91 = 91,
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SR92 = 92,
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SR93 = 93,
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SR94 = 94,
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SR95 = 95,
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SR_HWTASKID = 96,
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SR_CIRCULARQUEUEENTRYINDEX = 97,
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SR_CIRCULARQUEUEENTRYADDRESSLOW = 98,
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SR_CIRCULARQUEUEENTRYADDRESSHIGH = 99,
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};
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[[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) {
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@ -103,6 +133,16 @@ enum class SpecialRegister : u64 {
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return ir.Imm32(Common::BitCast<u32>(1.0f));
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case SpecialRegister::SR_LANEID:
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return ir.LaneId();
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case SpecialRegister::SR_EQMASK:
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return ir.SubgroupEqMask();
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case SpecialRegister::SR_LTMASK:
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return ir.SubgroupLtMask();
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case SpecialRegister::SR_LEMASK:
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return ir.SubgroupLeMask();
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case SpecialRegister::SR_GTMASK:
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return ir.SubgroupGtMask();
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case SpecialRegister::SR_GEMASK:
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return ir.SubgroupGeMask();
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default:
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throw NotImplementedException("S2R special register {}", special_register);
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}
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@ -414,6 +414,13 @@ void VisitUsages(Info& info, IR::Inst& inst) {
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inst.GetAssociatedPseudoOperation(IR::Opcode::GetSparseFromOp) != nullptr;
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break;
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}
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case IR::Opcode::SubgroupEqMask:
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case IR::Opcode::SubgroupLtMask:
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case IR::Opcode::SubgroupLeMask:
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case IR::Opcode::SubgroupGtMask:
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case IR::Opcode::SubgroupGeMask:
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info.uses_subgroup_mask = true;
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break;
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case IR::Opcode::VoteAll:
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case IR::Opcode::VoteAny:
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case IR::Opcode::VoteEqual:
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@ -99,6 +99,7 @@ struct Info {
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bool uses_sparse_residency{};
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bool uses_demote_to_helper_invocation{};
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bool uses_subgroup_vote{};
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bool uses_subgroup_mask{};
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bool uses_fswzadd{};
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IR::Type used_constant_buffer_types{};
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