Subv
dcae0c9a4f
GPU: Added the TSC registers to the Maxwell3D register structure.
2018-03-19 00:36:25 -05:00
Subv
cff7b29bba
GPU: Added the TIC registers to the Maxwell3D register structure.
2018-03-19 00:32:57 -05:00
Subv
03156d0c9a
GPU: Implement macro 0xE1A BindTextureInfoBuffer in HLE.
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This macro simply sets the current CB_ADDRESS to the texture buffer address for the input shader stage.
2018-03-18 19:03:40 -05:00
Subv
7b6868e908
GPU: Implement the BindStorageBuffer macro method in HLE.
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This macro binds the SSBO Info Buffer as the current ConstBuffer.
This buffer is usually bound to c0 during shader execution.
Games seem to use this macro instead of directly writing the address for some reason.
2018-03-18 16:50:42 -05:00
Subv
85d820b1b4
GPU: Handle writes to the CB_DATA method.
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Writing to this method will cause the written value to be stored in the currently-set ConstBuffer plus CB_POS.
This method is usually used to upload uniforms or other shader-visible data.
2018-03-18 15:23:24 -05:00
Subv
aa586fa268
GPU: Store uploaded GPU macros and keep track of the number of method parameters.
2018-03-18 11:51:46 -05:00
Subv
7ac8657432
GPU: Macros are specific to the Maxwell3D engine, so handle them internally.
2018-03-18 11:51:45 -05:00
Subv
ccb8da1512
GPU: Renamed ShaderType to ShaderStage as that is less confusing.
2018-03-17 18:32:57 -05:00
Subv
88698c156f
GPU: Store shader constbuffer bindings in the GPU state.
2018-03-17 18:32:57 -05:00
Subv
66dae22790
GPU: Corrected some register offsets and removed superfluous macro registers.
2018-03-17 18:32:56 -05:00
Subv
1d9d9c16e8
GPU: Make the SetShader macro call do the same as the real macro's code.
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It'll now set the CB_SIZE, CB_ADDRESS and CB_BIND registers when it's called.
Presumably this SetShader function is binding the constant shader uniforms to buffer 1 (c1[]).
2018-03-17 18:32:55 -05:00
Subv
579000e747
GPU: Corrected the parameter documentation for the SetShader macro call.
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Register 0xE24 is actually a macro that sets some shader parameters in the register structure.
Macros are uploaded to the GPU at startup and have their own ISA, we'll probably write an interpreter for this in the future.
2018-03-17 13:55:42 -05:00
bunnei
516ef4f19f
Merge pull request #242 from Subv/set_shader
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GPU: Handle the SetShader method call (0xE24) and store the shader config.
2018-03-17 00:34:17 -04:00
Subv
f93d769a1c
GPU: Handle the SetShader method call (0xE24) and store the shader config.
2018-03-16 22:51:06 -05:00
Subv
d2888f7e90
GPU: Added the vertex array registers.
2018-03-16 22:47:45 -05:00
bunnei
cd4e8a989c
Merge pull request #241 from Subv/gpu_method_call
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GPU: Process command mode 5 (IncreaseOnce) differently from other commands
2018-03-16 22:28:22 -04:00
Subv
29feece4b8
GPU: Process command mode 5 (IncreaseOnce) differently from other commands.
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Accumulate all arguments before calling the desired method.
Note: Maybe we should do the same for the NonIncreasing mode?
2018-03-16 20:32:44 -05:00
Subv
bf310a41b8
GPU: Assert that we get a 0 CODE_ADDRESS register in the 3D engine.
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Shader address calculation depends on this value to some extent, we do not currently know what it being 0 entails.
2018-03-16 19:24:41 -05:00
Subv
cbec739e7b
GPU: Added Maxwell registers for Shader Program control.
2018-03-16 19:23:11 -05:00
Subv
5fb4c718cc
GPU: Intercept writes to the VERTEX_END_GL register.
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This is the register that gets written after a game calls DrawArrays().
We should collect all GPU state and draw using our graphics API here.
2018-03-04 19:14:04 -05:00
Lioncash
490d0e36a0
maxwell_3d: Make constructor explicit
2018-02-13 23:47:51 -05:00
Subv
ac61a7d1e6
GPU: Partially implemented the QUERY_* registers in the Maxwell3D engine.
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Only QueryMode::Write is supported at the moment.
2018-02-12 12:34:41 -05:00
Subv
6cddf9d88e
Make a GPU class in VideoCore to contain the GPU state.
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Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there.
2018-02-11 23:44:12 -05:00
Subv
e01a8f2187
GPU: Added a command processor to decode the GPU pushbuffers and forward the commands to their respective engines.
2018-02-11 22:42:48 -05:00
