mirror of
https://github.com/starr-dusT/yuzu-mainline
synced 2024-03-05 21:12:25 -08:00
98e3274935
PDC0 and PDC1 are both VBlank interrupts. PDC0 was being treated as a HBlank interrupt and fired many more times than it should. They now both fire together at 60 Hz. This puzzlingly *improves* apparent framerate on many applications. A few other interrupts were being fired inside the GSP command processing instead of on the actual GPU register writes, so they were moved there, which should cover direct writes tho those registers not going through the GX command queue.
394 lines
16 KiB
C++
394 lines
16 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/log.h"
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#include "common/bit_field.h"
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#include "core/mem_map.h"
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#include "core/hle/kernel/event.h"
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#include "core/hle/kernel/shared_memory.h"
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#include "gsp_gpu.h"
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#include "core/hw/gpu.h"
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#include "video_core/gpu_debugger.h"
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// Main graphics debugger object - TODO: Here is probably not the best place for this
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GraphicsDebugger g_debugger;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Namespace GSP_GPU
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namespace GSP_GPU {
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Handle g_interrupt_event = 0; ///< Handle to event triggered when GSP interrupt has been signalled
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Handle g_shared_memory = 0; ///< Handle to GSP shared memorys
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u32 g_thread_id = 1; ///< Thread index into interrupt relay queue, 1 is arbitrary
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/// Gets a pointer to a thread command buffer in GSP shared memory
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static inline u8* GetCommandBuffer(u32 thread_id) {
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ResultVal<u8*> ptr = Kernel::GetSharedMemoryPointer(g_shared_memory, 0x800 + (thread_id * sizeof(CommandBuffer)));
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return ptr.ValueOr(nullptr);
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}
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static inline FrameBufferUpdate* GetFrameBufferInfo(u32 thread_id, u32 screen_index) {
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_dbg_assert_msg_(Service_GSP, screen_index < 2, "Invalid screen index");
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// For each thread there are two FrameBufferUpdate fields
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u32 offset = 0x200 + (2 * thread_id + screen_index) * sizeof(FrameBufferUpdate);
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ResultVal<u8*> ptr = Kernel::GetSharedMemoryPointer(g_shared_memory, offset);
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return reinterpret_cast<FrameBufferUpdate*>(ptr.ValueOr(nullptr));
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}
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/// Gets a pointer to the interrupt relay queue for a given thread index
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static inline InterruptRelayQueue* GetInterruptRelayQueue(u32 thread_id) {
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ResultVal<u8*> ptr = Kernel::GetSharedMemoryPointer(g_shared_memory, sizeof(InterruptRelayQueue) * thread_id);
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return reinterpret_cast<InterruptRelayQueue*>(ptr.ValueOr(nullptr));
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}
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static void WriteHWRegs(u32 base_address, u32 size_in_bytes, const u32* data) {
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// TODO: Return proper error codes
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if (base_address + size_in_bytes >= 0x420000) {
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LOG_ERROR(Service_GSP, "Write address out of range! (address=0x%08x, size=0x%08x)",
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base_address, size_in_bytes);
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return;
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}
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// size should be word-aligned
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if ((size_in_bytes % 4) != 0) {
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LOG_ERROR(Service_GSP, "Invalid size 0x%08x", size_in_bytes);
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return;
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}
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while (size_in_bytes > 0) {
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GPU::Write<u32>(base_address + 0x1EB00000, *data);
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size_in_bytes -= 4;
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++data;
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base_address += 4;
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}
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}
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/// Write a GSP GPU hardware register
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static void WriteHWRegs(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32* src = (u32*)Memory::GetPointer(cmd_buff[0x4]);
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WriteHWRegs(reg_addr, size, src);
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}
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/// Read a GSP GPU hardware register
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static void ReadHWRegs(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 reg_addr = cmd_buff[1];
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u32 size = cmd_buff[2];
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// TODO: Return proper error codes
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if (reg_addr + size >= 0x420000) {
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LOG_ERROR(Service_GSP, "Read address out of range! (address=0x%08x, size=0x%08x)", reg_addr, size);
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return;
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}
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// size should be word-aligned
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if ((size % 4) != 0) {
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LOG_ERROR(Service_GSP, "Invalid size 0x%08x", size);
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return;
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}
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u32* dst = (u32*)Memory::GetPointer(cmd_buff[0x41]);
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while (size > 0) {
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GPU::Read<u32>(*dst, reg_addr + 0x1EB00000);
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size -= 4;
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++dst;
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reg_addr += 4;
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}
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}
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static void SetBufferSwap(u32 screen_id, const FrameBufferInfo& info) {
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u32 base_address = 0x400000;
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if (info.active_fb == 0) {
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WriteHWRegs(base_address + 4 * GPU_REG_INDEX(framebuffer_config[screen_id].address_left1), 4, &info.address_left);
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WriteHWRegs(base_address + 4 * GPU_REG_INDEX(framebuffer_config[screen_id].address_right1), 4, &info.address_right);
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} else {
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WriteHWRegs(base_address + 4 * GPU_REG_INDEX(framebuffer_config[screen_id].address_left2), 4, &info.address_left);
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WriteHWRegs(base_address + 4 * GPU_REG_INDEX(framebuffer_config[screen_id].address_right2), 4, &info.address_right);
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}
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WriteHWRegs(base_address + 4 * GPU_REG_INDEX(framebuffer_config[screen_id].stride), 4, &info.stride);
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WriteHWRegs(base_address + 4 * GPU_REG_INDEX(framebuffer_config[screen_id].color_format), 4, &info.format);
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WriteHWRegs(base_address + 4 * GPU_REG_INDEX(framebuffer_config[screen_id].active_fb), 4, &info.shown_fb);
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}
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/**
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* GSP_GPU::SetBufferSwap service function
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*
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* Updates GPU display framebuffer configuration using the specified parameters.
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*
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* Inputs:
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* 1 : Screen ID (0 = top screen, 1 = bottom screen)
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* 2-7 : FrameBufferInfo structure
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* Outputs:
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* 1: Result code
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*/
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static void SetBufferSwap(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 screen_id = cmd_buff[1];
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FrameBufferInfo* fb_info = (FrameBufferInfo*)&cmd_buff[2];
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SetBufferSwap(screen_id, *fb_info);
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cmd_buff[1] = 0; // No error
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}
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/**
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* GSP_GPU::FlushDataCache service function
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*
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* This Function is a no-op, We aren't emulating the CPU cache any time soon.
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*
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* Inputs:
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* 1 : Address
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* 2 : Size
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* 3 : Value 0, some descriptor for the KProcess Handle
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* 4 : KProcess handle
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* Outputs:
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* 1 : Result of function, 0 on success, otherwise error code
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*/
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static void FlushDataCache(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 address = cmd_buff[1];
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u32 size = cmd_buff[2];
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u32 process = cmd_buff[4];
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// TODO(purpasmart96): Verify return header on HW
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cmd_buff[1] = RESULT_SUCCESS.raw; // No error
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}
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/**
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* GSP_GPU::RegisterInterruptRelayQueue service function
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* Inputs:
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* 1 : "Flags" field, purpose is unknown
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* 3 : Handle to GSP synchronization event
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* Outputs:
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* 0 : Result of function, 0 on success, otherwise error code
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* 2 : Thread index into GSP command buffer
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* 4 : Handle to GSP shared memory
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*/
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static void RegisterInterruptRelayQueue(Service::Interface* self) {
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u32* cmd_buff = Kernel::GetCommandBuffer();
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u32 flags = cmd_buff[1];
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g_interrupt_event = cmd_buff[3];
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g_shared_memory = Kernel::CreateSharedMemory("GSPSharedMem");
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_assert_msg_(GSP, (g_interrupt_event != 0), "handle is not valid!");
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cmd_buff[1] = 0x2A07; // Value verified by 3dmoo team, purpose unknown, but needed for GSP init
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cmd_buff[2] = g_thread_id++; // Thread ID
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cmd_buff[4] = g_shared_memory; // GSP shared memory
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Kernel::SignalEvent(g_interrupt_event); // TODO(bunnei): Is this correct?
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}
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/**
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* Signals that the specified interrupt type has occurred to userland code
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* @param interrupt_id ID of interrupt that is being signalled
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* @todo This should probably take a thread_id parameter and only signal this thread?
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* @todo This probably does not belong in the GSP module, instead move to video_core
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*/
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void SignalInterrupt(InterruptId interrupt_id) {
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if (0 == g_interrupt_event) {
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LOG_WARNING(Service_GSP, "cannot synchronize until GSP event has been created!");
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return;
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}
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if (0 == g_shared_memory) {
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LOG_WARNING(Service_GSP, "cannot synchronize until GSP shared memory has been created!");
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return;
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}
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for (int thread_id = 0; thread_id < 0x4; ++thread_id) {
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InterruptRelayQueue* interrupt_relay_queue = GetInterruptRelayQueue(thread_id);
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interrupt_relay_queue->number_interrupts = interrupt_relay_queue->number_interrupts + 1;
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u8 next = interrupt_relay_queue->index;
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next += interrupt_relay_queue->number_interrupts;
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next = next % 0x34; // 0x34 is the number of interrupt slots
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interrupt_relay_queue->slot[next] = interrupt_id;
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interrupt_relay_queue->error_code = 0x0; // No error
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}
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Kernel::SignalEvent(g_interrupt_event);
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}
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/// Executes the next GSP command
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static void ExecuteCommand(const Command& command, u32 thread_id) {
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// Utility function to convert register ID to address
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auto WriteGPURegister = [](u32 id, u32 data) {
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GPU::Write<u32>(0x1EF00000 + 4 * id, data);
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};
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switch (command.id) {
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// GX request DMA - typically used for copying memory from GSP heap to VRAM
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case CommandId::REQUEST_DMA:
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memcpy(Memory::GetPointer(command.dma_request.dest_address),
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Memory::GetPointer(command.dma_request.source_address),
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command.dma_request.size);
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SignalInterrupt(InterruptId::DMA);
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break;
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// ctrulib homebrew sends all relevant command list data with this command,
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// hence we do all "interesting" stuff here and do nothing in SET_COMMAND_LIST_FIRST.
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// TODO: This will need some rework in the future.
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case CommandId::SET_COMMAND_LIST_LAST:
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{
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auto& params = command.set_command_list_last;
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WriteGPURegister(GPU_REG_INDEX(command_processor_config.address), Memory::VirtualToPhysicalAddress(params.address) >> 3);
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WriteGPURegister(GPU_REG_INDEX(command_processor_config.size), params.size);
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// TODO: Not sure if we are supposed to always write this .. seems to trigger processing though
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WriteGPURegister(GPU_REG_INDEX(command_processor_config.trigger), 1);
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break;
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}
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// It's assumed that the two "blocks" behave equivalently.
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// Presumably this is done simply to allow two memory fills to run in parallel.
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case CommandId::SET_MEMORY_FILL:
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{
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auto& params = command.memory_fill;
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[0].address_start), Memory::VirtualToPhysicalAddress(params.start1) >> 3);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[0].address_end), Memory::VirtualToPhysicalAddress(params.end1) >> 3);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[0].size), params.end1 - params.start1);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[0].value), params.value1);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].address_start), Memory::VirtualToPhysicalAddress(params.start2) >> 3);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].address_end), Memory::VirtualToPhysicalAddress(params.end2) >> 3);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].size), params.end2 - params.start2);
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WriteGPURegister(GPU_REG_INDEX(memory_fill_config[1].value), params.value2);
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break;
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}
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case CommandId::SET_DISPLAY_TRANSFER:
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{
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auto& params = command.image_copy;
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.input_address), Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_address), Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.input_size), params.in_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_size), params.out_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.flags), params.flags);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.trigger), 1);
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// Update framebuffer information if requested
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for (int screen_id = 0; screen_id < 2; ++screen_id) {
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FrameBufferUpdate* info = GetFrameBufferInfo(thread_id, screen_id);
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if (info->is_dirty) {
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SetBufferSwap(screen_id, info->framebuffer_info[info->index]);
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info->framebuffer_info->active_fb = info->framebuffer_info->active_fb ^ 1;
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}
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info->is_dirty = false;
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}
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break;
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}
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// TODO: Check if texture copies are implemented correctly..
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case CommandId::SET_TEXTURE_COPY:
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{
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auto& params = command.image_copy;
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.input_address), Memory::VirtualToPhysicalAddress(params.in_buffer_address) >> 3);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_address), Memory::VirtualToPhysicalAddress(params.out_buffer_address) >> 3);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.input_size), params.in_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.output_size), params.out_buffer_size);
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.flags), params.flags);
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// TODO: Should this register be set to 1 or should instead its value be OR-ed with 1?
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WriteGPURegister(GPU_REG_INDEX(display_transfer_config.trigger), 1);
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break;
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}
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// TODO: Figure out what exactly SET_COMMAND_LIST_FIRST and SET_COMMAND_LIST_LAST
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// are supposed to do.
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case CommandId::SET_COMMAND_LIST_FIRST:
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{
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break;
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}
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default:
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LOG_ERROR(Service_GSP, "unknown command 0x%08X", (int)command.id.Value());
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}
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}
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/// This triggers handling of the GX command written to the command buffer in shared memory.
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static void TriggerCmdReqQueue(Service::Interface* self) {
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// Iterate through each thread's command queue...
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for (unsigned thread_id = 0; thread_id < 0x4; ++thread_id) {
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CommandBuffer* command_buffer = (CommandBuffer*)GetCommandBuffer(thread_id);
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// Iterate through each command...
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for (unsigned i = 0; i < command_buffer->number_commands; ++i) {
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g_debugger.GXCommandProcessed((u8*)&command_buffer->commands[i]);
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// Decode and execute command
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ExecuteCommand(command_buffer->commands[i], thread_id);
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// Indicates that command has completed
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command_buffer->number_commands = command_buffer->number_commands - 1;
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}
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}
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u32* cmd_buff = Kernel::GetCommandBuffer();
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cmd_buff[1] = 0; // No error
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}
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const Interface::FunctionInfo FunctionTable[] = {
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{0x00010082, WriteHWRegs, "WriteHWRegs"},
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{0x00020084, nullptr, "WriteHWRegsWithMask"},
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{0x00030082, nullptr, "WriteHWRegRepeat"},
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{0x00040080, ReadHWRegs, "ReadHWRegs"},
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{0x00050200, SetBufferSwap, "SetBufferSwap"},
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{0x00060082, nullptr, "SetCommandList"},
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{0x000700C2, nullptr, "RequestDma"},
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{0x00080082, FlushDataCache, "FlushDataCache"},
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{0x00090082, nullptr, "InvalidateDataCache"},
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{0x000A0044, nullptr, "RegisterInterruptEvents"},
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{0x000B0040, nullptr, "SetLcdForceBlack"},
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{0x000C0000, TriggerCmdReqQueue, "TriggerCmdReqQueue"},
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{0x000D0140, nullptr, "SetDisplayTransfer"},
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{0x000E0180, nullptr, "SetTextureCopy"},
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{0x000F0200, nullptr, "SetMemoryFill"},
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{0x00100040, nullptr, "SetAxiConfigQoSMode"},
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{0x00110040, nullptr, "SetPerfLogMode"},
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{0x00120000, nullptr, "GetPerfLog"},
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{0x00130042, RegisterInterruptRelayQueue, "RegisterInterruptRelayQueue"},
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{0x00140000, nullptr, "UnregisterInterruptRelayQueue"},
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{0x00150002, nullptr, "TryAcquireRight"},
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{0x00160042, nullptr, "AcquireRight"},
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{0x00170000, nullptr, "ReleaseRight"},
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{0x00180000, nullptr, "ImportDisplayCaptureInfo"},
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{0x00190000, nullptr, "SaveVramSysArea"},
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{0x001A0000, nullptr, "RestoreVramSysArea"},
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{0x001B0000, nullptr, "ResetGpuCore"},
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{0x001C0040, nullptr, "SetLedForceOff"},
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{0x001D0040, nullptr, "SetTestCommand"},
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{0x001E0080, nullptr, "SetInternalPriorities"},
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{0x001F0082, nullptr, "StoreDataCache"},
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};
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////////////////////////////////////////////////////////////////////////////////////////////////////
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// Interface class
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Interface::Interface() {
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Register(FunctionTable, ARRAY_SIZE(FunctionTable));
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g_interrupt_event = 0;
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g_shared_memory = 0;
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g_thread_id = 1;
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}
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} // namespace
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