2022-04-23 01:59:50 -07:00
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// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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2018-03-18 13:15:05 -07:00
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2021-09-30 21:57:02 -07:00
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#include <array>
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#include <atomic>
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2020-02-24 18:04:12 -08:00
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#include <chrono>
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#include <condition_variable>
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#include <list>
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#include <memory>
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2020-02-24 18:04:12 -08:00
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2018-08-10 15:39:37 -07:00
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#include "common/assert.h"
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2019-09-25 16:43:23 -07:00
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#include "common/microprofile.h"
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#include "common/settings.h"
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2019-02-14 09:42:58 -08:00
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#include "core/core.h"
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2019-01-29 18:49:18 -08:00
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#include "core/core_timing.h"
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#include "core/frontend/emu_window.h"
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#include "core/hle/service/nvdrv/nvdata.h"
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#include "core/perf_stats.h"
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#include "video_core/cdma_pusher.h"
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#include "video_core/control/channel_state.h"
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#include "video_core/control/scheduler.h"
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#include "video_core/dma_pusher.h"
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#include "video_core/engines/fermi_2d.h"
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2019-01-22 15:49:31 -08:00
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#include "video_core/engines/kepler_compute.h"
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#include "video_core/engines/kepler_memory.h"
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#include "video_core/engines/maxwell_3d.h"
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2018-06-10 15:02:33 -07:00
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#include "video_core/engines/maxwell_dma.h"
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#include "video_core/gpu.h"
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#include "video_core/gpu_thread.h"
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#include "video_core/host1x/host1x.h"
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#include "video_core/host1x/syncpoint_manager.h"
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#include "video_core/memory_manager.h"
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#include "video_core/renderer_base.h"
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#include "video_core/shader_notify.h"
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2018-03-18 13:15:05 -07:00
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namespace Tegra {
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struct GPU::Impl {
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explicit Impl(GPU& gpu_, Core::System& system_, bool is_async_, bool use_nvdec_)
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: gpu{gpu_}, system{system_}, host1x{system.Host1x()}, use_nvdec{use_nvdec_},
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shader_notify{std::make_unique<VideoCore::ShaderNotify>()}, is_async{is_async_},
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gpu_thread{system_, is_async_}, scheduler{std::make_unique<Control::Scheduler>(gpu)} {}
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~Impl() = default;
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std::shared_ptr<Control::ChannelState> CreateChannel(s32 channel_id) {
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auto channel_state = std::make_shared<Tegra::Control::ChannelState>(channel_id);
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channels.emplace(channel_id, channel_state);
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scheduler->DeclareChannel(channel_state);
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return channel_state;
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}
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void BindChannel(s32 channel_id) {
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if (bound_channel == channel_id) {
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return;
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}
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auto it = channels.find(channel_id);
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ASSERT(it != channels.end());
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bound_channel = channel_id;
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current_channel = it->second.get();
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rasterizer->BindChannel(*current_channel);
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}
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std::shared_ptr<Control::ChannelState> AllocateChannel() {
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return CreateChannel(new_channel_id++);
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}
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void InitChannel(Control::ChannelState& to_init) {
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to_init.Init(system, gpu);
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to_init.BindRasterizer(rasterizer);
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rasterizer->InitializeChannel(to_init);
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}
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void InitAddressSpace(Tegra::MemoryManager& memory_manager) {
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memory_manager.BindRasterizer(rasterizer);
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}
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void ReleaseChannel(Control::ChannelState& to_release) {
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UNIMPLEMENTED();
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}
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/// Binds a renderer to the GPU.
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void BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer_) {
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renderer = std::move(renderer_);
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rasterizer = renderer->ReadRasterizer();
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host1x.MemoryManager().BindRasterizer(rasterizer);
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}
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/// Flush all current written commands into the host GPU for execution.
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void FlushCommands() {
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rasterizer->FlushCommands();
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}
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/// Synchronizes CPU writes with Host GPU memory.
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void InvalidateGPUCache() {
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rasterizer->InvalidateGPUCache();
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}
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/// Signal the ending of command list.
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void OnCommandListEnd() {
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gpu_thread.OnCommandListEnd();
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}
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/// Request a host GPU memory flush from the CPU.
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template <typename Func>
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[[nodiscard]] u64 RequestSyncOperation(Func&& action) {
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std::unique_lock lck{sync_request_mutex};
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const u64 fence = ++last_sync_fence;
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sync_requests.emplace_back(action);
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return fence;
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}
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/// Obtains current flush request fence id.
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[[nodiscard]] u64 CurrentSyncRequestFence() const {
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return current_sync_fence.load(std::memory_order_relaxed);
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}
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void WaitForSyncOperation(const u64 fence) {
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std::unique_lock lck{sync_request_mutex};
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sync_request_cv.wait(lck, [this, fence] { return CurrentSyncRequestFence() >= fence; });
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}
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/// Tick pending requests within the GPU.
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void TickWork() {
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std::unique_lock lck{sync_request_mutex};
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while (!sync_requests.empty()) {
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auto request = std::move(sync_requests.front());
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sync_requests.pop_front();
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sync_request_mutex.unlock();
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request();
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current_sync_fence.fetch_add(1, std::memory_order_release);
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sync_request_mutex.lock();
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sync_request_cv.notify_all();
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}
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}
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/// Returns a reference to the Maxwell3D GPU engine.
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[[nodiscard]] Engines::Maxwell3D& Maxwell3D() {
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ASSERT(current_channel);
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return *current_channel->maxwell_3d;
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}
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/// Returns a const reference to the Maxwell3D GPU engine.
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[[nodiscard]] const Engines::Maxwell3D& Maxwell3D() const {
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ASSERT(current_channel);
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return *current_channel->maxwell_3d;
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}
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] Engines::KeplerCompute& KeplerCompute() {
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ASSERT(current_channel);
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return *current_channel->kepler_compute;
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}
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/// Returns a reference to the KeplerCompute GPU engine.
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[[nodiscard]] const Engines::KeplerCompute& KeplerCompute() const {
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ASSERT(current_channel);
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return *current_channel->kepler_compute;
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}
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/// Returns a reference to the GPU DMA pusher.
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[[nodiscard]] Tegra::DmaPusher& DmaPusher() {
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ASSERT(current_channel);
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return *current_channel->dma_pusher;
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}
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/// Returns a const reference to the GPU DMA pusher.
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[[nodiscard]] const Tegra::DmaPusher& DmaPusher() const {
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ASSERT(current_channel);
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return *current_channel->dma_pusher;
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}
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/// Returns a reference to the underlying renderer.
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[[nodiscard]] VideoCore::RendererBase& Renderer() {
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return *renderer;
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}
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/// Returns a const reference to the underlying renderer.
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[[nodiscard]] const VideoCore::RendererBase& Renderer() const {
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return *renderer;
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}
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/// Returns a reference to the shader notifier.
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[[nodiscard]] VideoCore::ShaderNotify& ShaderNotify() {
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return *shader_notify;
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}
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/// Returns a const reference to the shader notifier.
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[[nodiscard]] const VideoCore::ShaderNotify& ShaderNotify() const {
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return *shader_notify;
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}
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[[nodiscard]] u64 GetTicks() const {
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// This values were reversed engineered by fincs from NVN
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// The gpu clock is reported in units of 385/625 nanoseconds
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constexpr u64 gpu_ticks_num = 384;
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constexpr u64 gpu_ticks_den = 625;
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u64 nanoseconds = system.CoreTiming().GetGlobalTimeNs().count();
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if (Settings::values.use_fast_gpu_time.GetValue()) {
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nanoseconds /= 256;
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}
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const u64 nanoseconds_num = nanoseconds / gpu_ticks_den;
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const u64 nanoseconds_rem = nanoseconds % gpu_ticks_den;
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return nanoseconds_num * gpu_ticks_num + (nanoseconds_rem * gpu_ticks_num) / gpu_ticks_den;
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}
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[[nodiscard]] bool IsAsync() const {
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return is_async;
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}
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[[nodiscard]] bool UseNvdec() const {
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return use_nvdec;
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}
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void RendererFrameEndNotify() {
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system.GetPerfStats().EndGameFrame();
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}
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/// Performs any additional setup necessary in order to begin GPU emulation.
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/// This can be used to launch any necessary threads and register any necessary
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/// core timing events.
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void Start() {
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gpu_thread.StartThread(*renderer, renderer->Context(), *scheduler);
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cpu_context = renderer->GetRenderWindow().CreateSharedContext();
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cpu_context->MakeCurrent();
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}
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2022-01-03 17:31:51 -08:00
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void NotifyShutdown() {
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std::unique_lock lk{sync_mutex};
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shutting_down.store(true, std::memory_order::relaxed);
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sync_cv.notify_all();
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}
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/// Obtain the CPU Context
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void ObtainContext() {
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cpu_context->MakeCurrent();
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}
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/// Release the CPU Context
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void ReleaseContext() {
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cpu_context->DoneCurrent();
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}
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/// Push GPU command entries to be processed
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void PushGPUEntries(s32 channel, Tegra::CommandList&& entries) {
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gpu_thread.SubmitList(channel, std::move(entries));
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}
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/// Push GPU command buffer entries to be processed
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void PushCommandBuffer(u32 id, Tegra::ChCommandHeaderList& entries) {
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if (!use_nvdec) {
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return;
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}
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if (!cdma_pushers.contains(id)) {
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cdma_pushers.insert_or_assign(id, std::make_unique<Tegra::CDmaPusher>(host1x));
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}
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// SubmitCommandBuffer would make the nvdec operations async, this is not currently working
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// TODO(ameerj): RE proper async nvdec operation
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// gpu_thread.SubmitCommandBuffer(std::move(entries));
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cdma_pushers[id]->ProcessEntries(std::move(entries));
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}
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/// Frees the CDMAPusher instance to free up resources
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void ClearCdmaInstance(u32 id) {
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const auto iter = cdma_pushers.find(id);
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if (iter != cdma_pushers.end()) {
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cdma_pushers.erase(iter);
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}
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}
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/// Swap buffers (render frame)
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void SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
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gpu_thread.SwapBuffers(framebuffer);
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}
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/// Notify rasterizer that any caches of the specified region should be flushed to Switch memory
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void FlushRegion(VAddr addr, u64 size) {
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gpu_thread.FlushRegion(addr, size);
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}
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/// Notify rasterizer that any caches of the specified region should be invalidated
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void InvalidateRegion(VAddr addr, u64 size) {
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gpu_thread.InvalidateRegion(addr, size);
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}
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/// Notify rasterizer that any caches of the specified region should be flushed and invalidated
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void FlushAndInvalidateRegion(VAddr addr, u64 size) {
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gpu_thread.FlushAndInvalidateRegion(addr, size);
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}
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2022-01-30 01:31:13 -08:00
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void RequestSwapBuffers(const Tegra::FramebufferConfig* framebuffer,
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std::array<Service::Nvidia::NvFence, 4>& fences, size_t num_fences) {
|
2022-01-30 01:31:13 -08:00
|
|
|
size_t current_request_counter{};
|
|
|
|
{
|
|
|
|
std::unique_lock<std::mutex> lk(request_swap_mutex);
|
|
|
|
if (free_swap_counters.empty()) {
|
|
|
|
current_request_counter = request_swap_counters.size();
|
|
|
|
request_swap_counters.emplace_back(num_fences);
|
|
|
|
} else {
|
|
|
|
current_request_counter = free_swap_counters.front();
|
|
|
|
request_swap_counters[current_request_counter] = num_fences;
|
|
|
|
free_swap_counters.pop_front();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
const auto wait_fence =
|
|
|
|
RequestSyncOperation([this, current_request_counter, framebuffer, fences, num_fences] {
|
|
|
|
auto& syncpoint_manager = host1x.GetSyncpointManager();
|
|
|
|
if (num_fences == 0) {
|
|
|
|
renderer->SwapBuffers(framebuffer);
|
|
|
|
}
|
|
|
|
const auto executer = [this, current_request_counter,
|
|
|
|
framebuffer_copy = *framebuffer]() {
|
|
|
|
{
|
|
|
|
std::unique_lock<std::mutex> lk(request_swap_mutex);
|
|
|
|
if (--request_swap_counters[current_request_counter] != 0) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
free_swap_counters.push_back(current_request_counter);
|
|
|
|
}
|
|
|
|
renderer->SwapBuffers(&framebuffer_copy);
|
|
|
|
};
|
|
|
|
for (size_t i = 0; i < num_fences; i++) {
|
|
|
|
syncpoint_manager.RegisterGuestAction(fences[i].id, fences[i].value, executer);
|
|
|
|
}
|
|
|
|
});
|
|
|
|
gpu_thread.TickGPU();
|
|
|
|
WaitForSyncOperation(wait_fence);
|
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
GPU& gpu;
|
|
|
|
Core::System& system;
|
2022-01-30 01:31:13 -08:00
|
|
|
Host1x::Host1x& host1x;
|
2021-11-05 07:52:31 -07:00
|
|
|
|
2021-12-01 20:19:43 -08:00
|
|
|
std::map<u32, std::unique_ptr<Tegra::CDmaPusher>> cdma_pushers;
|
2021-09-30 21:57:02 -07:00
|
|
|
std::unique_ptr<VideoCore::RendererBase> renderer;
|
|
|
|
VideoCore::RasterizerInterface* rasterizer = nullptr;
|
|
|
|
const bool use_nvdec;
|
|
|
|
|
2021-11-05 07:52:31 -07:00
|
|
|
s32 new_channel_id{1};
|
2021-09-30 21:57:02 -07:00
|
|
|
/// Shader build notifier
|
|
|
|
std::unique_ptr<VideoCore::ShaderNotify> shader_notify;
|
2022-01-03 17:28:54 -08:00
|
|
|
/// When true, we are about to shut down emulation session, so terminate outstanding tasks
|
|
|
|
std::atomic_bool shutting_down{};
|
2021-09-30 21:57:02 -07:00
|
|
|
|
|
|
|
std::array<std::atomic<u32>, Service::Nvidia::MaxSyncPoints> syncpoints{};
|
|
|
|
|
|
|
|
std::array<std::list<u32>, Service::Nvidia::MaxSyncPoints> syncpt_interrupts;
|
|
|
|
|
|
|
|
std::mutex sync_mutex;
|
|
|
|
std::mutex device_mutex;
|
|
|
|
|
2022-01-03 17:28:54 -08:00
|
|
|
std::condition_variable sync_cv;
|
2021-09-30 21:57:02 -07:00
|
|
|
|
2022-08-31 20:45:22 -07:00
|
|
|
std::list<std::function<void()>> sync_requests;
|
2022-01-30 01:31:13 -08:00
|
|
|
std::atomic<u64> current_sync_fence{};
|
|
|
|
u64 last_sync_fence{};
|
|
|
|
std::mutex sync_request_mutex;
|
|
|
|
std::condition_variable sync_request_cv;
|
2021-09-30 21:57:02 -07:00
|
|
|
|
|
|
|
const bool is_async;
|
|
|
|
|
|
|
|
VideoCommon::GPUThread::ThreadManager gpu_thread;
|
|
|
|
std::unique_ptr<Core::Frontend::GraphicsContext> cpu_context;
|
|
|
|
|
2021-11-05 07:52:31 -07:00
|
|
|
std::unique_ptr<Tegra::Control::Scheduler> scheduler;
|
|
|
|
std::unordered_map<s32, std::shared_ptr<Tegra::Control::ChannelState>> channels;
|
|
|
|
Tegra::Control::ChannelState* current_channel;
|
|
|
|
s32 bound_channel{-1};
|
2022-01-30 01:31:13 -08:00
|
|
|
|
|
|
|
std::deque<size_t> free_swap_counters;
|
|
|
|
std::deque<size_t> request_swap_counters;
|
|
|
|
std::mutex request_swap_mutex;
|
2021-09-30 21:57:02 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
GPU::GPU(Core::System& system, bool is_async, bool use_nvdec)
|
|
|
|
: impl{std::make_unique<Impl>(*this, system, is_async, use_nvdec)} {}
|
2018-03-18 13:15:05 -07:00
|
|
|
|
|
|
|
GPU::~GPU() = default;
|
|
|
|
|
2021-11-05 07:52:31 -07:00
|
|
|
std::shared_ptr<Control::ChannelState> GPU::AllocateChannel() {
|
|
|
|
return impl->AllocateChannel();
|
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::InitChannel(Control::ChannelState& to_init) {
|
|
|
|
impl->InitChannel(to_init);
|
2021-09-30 21:57:02 -07:00
|
|
|
}
|
2020-06-10 20:58:57 -07:00
|
|
|
|
2021-11-05 07:52:31 -07:00
|
|
|
void GPU::BindChannel(s32 channel_id) {
|
|
|
|
impl->BindChannel(channel_id);
|
2020-06-10 20:58:57 -07:00
|
|
|
}
|
|
|
|
|
2021-11-05 07:52:31 -07:00
|
|
|
void GPU::ReleaseChannel(Control::ChannelState& to_release) {
|
|
|
|
impl->ReleaseChannel(to_release);
|
|
|
|
}
|
|
|
|
|
2022-01-01 13:03:37 -08:00
|
|
|
void GPU::InitAddressSpace(Tegra::MemoryManager& memory_manager) {
|
|
|
|
impl->InitAddressSpace(memory_manager);
|
|
|
|
}
|
|
|
|
|
2021-11-05 07:52:31 -07:00
|
|
|
void GPU::BindRenderer(std::unique_ptr<VideoCore::RendererBase> renderer) {
|
|
|
|
impl->BindRenderer(std::move(renderer));
|
2018-07-20 15:31:36 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
void GPU::FlushCommands() {
|
|
|
|
impl->FlushCommands();
|
2018-03-22 13:19:35 -07:00
|
|
|
}
|
|
|
|
|
2022-02-05 16:16:11 -08:00
|
|
|
void GPU::InvalidateGPUCache() {
|
|
|
|
impl->InvalidateGPUCache();
|
2019-07-14 18:25:13 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
void GPU::OnCommandListEnd() {
|
|
|
|
impl->OnCommandListEnd();
|
2019-07-14 18:25:13 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
u64 GPU::RequestFlush(VAddr addr, std::size_t size) {
|
2022-01-30 01:31:13 -08:00
|
|
|
return impl->RequestSyncOperation(
|
|
|
|
[this, addr, size]() { impl->rasterizer->FlushRegion(addr, size); });
|
|
|
|
}
|
|
|
|
|
|
|
|
u64 GPU::CurrentSyncRequestFence() const {
|
|
|
|
return impl->CurrentSyncRequestFence();
|
2018-08-28 07:57:56 -07:00
|
|
|
}
|
|
|
|
|
2022-01-30 01:31:13 -08:00
|
|
|
void GPU::WaitForSyncOperation(u64 fence) {
|
|
|
|
return impl->WaitForSyncOperation(fence);
|
2018-08-28 07:57:56 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
void GPU::TickWork() {
|
|
|
|
impl->TickWork();
|
2018-11-23 20:20:56 -08:00
|
|
|
}
|
|
|
|
|
2022-01-30 01:31:13 -08:00
|
|
|
/// Gets a mutable reference to the Host1x interface
|
|
|
|
Host1x::Host1x& GPU::Host1x() {
|
|
|
|
return impl->host1x;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Gets an immutable reference to the Host1x interface.
|
|
|
|
const Host1x::Host1x& GPU::Host1x() const {
|
|
|
|
return impl->host1x;
|
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
Engines::Maxwell3D& GPU::Maxwell3D() {
|
|
|
|
return impl->Maxwell3D();
|
2020-10-26 20:07:36 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
const Engines::Maxwell3D& GPU::Maxwell3D() const {
|
|
|
|
return impl->Maxwell3D();
|
2018-11-23 20:20:56 -08:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
Engines::KeplerCompute& GPU::KeplerCompute() {
|
|
|
|
return impl->KeplerCompute();
|
2020-10-26 20:07:36 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
const Engines::KeplerCompute& GPU::KeplerCompute() const {
|
|
|
|
return impl->KeplerCompute();
|
2019-06-07 09:56:30 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
Tegra::DmaPusher& GPU::DmaPusher() {
|
|
|
|
return impl->DmaPusher();
|
|
|
|
}
|
2019-06-18 17:53:21 -07:00
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
const Tegra::DmaPusher& GPU::DmaPusher() const {
|
|
|
|
return impl->DmaPusher();
|
2019-06-07 18:13:20 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
VideoCore::RendererBase& GPU::Renderer() {
|
|
|
|
return impl->Renderer();
|
|
|
|
}
|
2020-02-13 14:16:07 -08:00
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
const VideoCore::RendererBase& GPU::Renderer() const {
|
|
|
|
return impl->Renderer();
|
2020-02-10 06:32:51 -08:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
VideoCore::ShaderNotify& GPU::ShaderNotify() {
|
|
|
|
return impl->ShaderNotify();
|
2021-05-15 17:34:20 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
const VideoCore::ShaderNotify& GPU::ShaderNotify() const {
|
|
|
|
return impl->ShaderNotify();
|
2019-07-26 11:20:43 -07:00
|
|
|
}
|
|
|
|
|
2022-01-30 01:31:13 -08:00
|
|
|
void GPU::RequestSwapBuffers(const Tegra::FramebufferConfig* framebuffer,
|
2022-02-05 16:16:11 -08:00
|
|
|
std::array<Service::Nvidia::NvFence, 4>& fences, size_t num_fences) {
|
2022-01-30 01:31:13 -08:00
|
|
|
impl->RequestSwapBuffers(framebuffer, fences, num_fences);
|
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
u64 GPU::GetTicks() const {
|
|
|
|
return impl->GetTicks();
|
2020-04-19 23:16:56 -07:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
bool GPU::IsAsync() const {
|
|
|
|
return impl->IsAsync();
|
2019-01-29 18:49:18 -08:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
bool GPU::UseNvdec() const {
|
|
|
|
return impl->UseNvdec();
|
2019-01-29 18:49:18 -08:00
|
|
|
}
|
|
|
|
|
2021-09-30 21:57:02 -07:00
|
|
|
void GPU::RendererFrameEndNotify() {
|
|
|
|
impl->RendererFrameEndNotify();
|
2019-01-29 18:49:18 -08:00
|
|
|
}
|
|
|
|
|
2020-12-11 22:26:14 -08:00
|
|
|
void GPU::Start() {
|
2021-09-30 21:57:02 -07:00
|
|
|
impl->Start();
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
2022-01-03 17:31:51 -08:00
|
|
|
void GPU::NotifyShutdown() {
|
|
|
|
impl->NotifyShutdown();
|
|
|
|
}
|
|
|
|
|
2020-12-11 22:26:14 -08:00
|
|
|
void GPU::ObtainContext() {
|
2021-09-30 21:57:02 -07:00
|
|
|
impl->ObtainContext();
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::ReleaseContext() {
|
2021-09-30 21:57:02 -07:00
|
|
|
impl->ReleaseContext();
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
2021-11-05 07:52:31 -07:00
|
|
|
void GPU::PushGPUEntries(s32 channel, Tegra::CommandList&& entries) {
|
|
|
|
impl->PushGPUEntries(channel, std::move(entries));
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
2021-12-01 20:19:43 -08:00
|
|
|
void GPU::PushCommandBuffer(u32 id, Tegra::ChCommandHeaderList& entries) {
|
|
|
|
impl->PushCommandBuffer(id, entries);
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
2021-12-01 20:19:43 -08:00
|
|
|
void GPU::ClearCdmaInstance(u32 id) {
|
|
|
|
impl->ClearCdmaInstance(id);
|
2021-03-30 02:37:40 -07:00
|
|
|
}
|
|
|
|
|
2020-12-11 22:26:14 -08:00
|
|
|
void GPU::SwapBuffers(const Tegra::FramebufferConfig* framebuffer) {
|
2021-09-30 21:57:02 -07:00
|
|
|
impl->SwapBuffers(framebuffer);
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::FlushRegion(VAddr addr, u64 size) {
|
2021-09-30 21:57:02 -07:00
|
|
|
impl->FlushRegion(addr, size);
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::InvalidateRegion(VAddr addr, u64 size) {
|
2021-09-30 21:57:02 -07:00
|
|
|
impl->InvalidateRegion(addr, size);
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
void GPU::FlushAndInvalidateRegion(VAddr addr, u64 size) {
|
2021-09-30 21:57:02 -07:00
|
|
|
impl->FlushAndInvalidateRegion(addr, size);
|
2020-12-11 22:26:14 -08:00
|
|
|
}
|
|
|
|
|
2018-03-18 13:15:05 -07:00
|
|
|
} // namespace Tegra
|