2018-12-20 14:09:21 -08:00
|
|
|
// Copyright 2018 yuzu Emulator Project
|
|
|
|
// Licensed under GPLv2 or any later version
|
|
|
|
// Refer to the license.txt file included.
|
|
|
|
|
|
|
|
#include <cstring>
|
|
|
|
#include <set>
|
|
|
|
|
|
|
|
#include <fmt/format.h>
|
|
|
|
|
2018-12-20 22:18:54 -08:00
|
|
|
#include "common/assert.h"
|
2018-12-20 14:09:21 -08:00
|
|
|
#include "common/common_types.h"
|
|
|
|
#include "video_core/engines/shader_bytecode.h"
|
|
|
|
#include "video_core/engines/shader_header.h"
|
2019-06-24 16:46:49 -07:00
|
|
|
#include "video_core/shader/control_flow.h"
|
2019-06-04 18:44:06 -07:00
|
|
|
#include "video_core/shader/node_helper.h"
|
2018-12-20 14:09:21 -08:00
|
|
|
#include "video_core/shader/shader_ir.h"
|
|
|
|
|
|
|
|
namespace VideoCommon::Shader {
|
|
|
|
|
|
|
|
using Tegra::Shader::Instruction;
|
|
|
|
using Tegra::Shader::OpCode;
|
|
|
|
|
2018-12-20 22:39:46 -08:00
|
|
|
namespace {
|
|
|
|
|
2018-12-20 14:09:21 -08:00
|
|
|
/**
|
|
|
|
* Returns whether the instruction at the specified offset is a 'sched' instruction.
|
|
|
|
* Sched instructions always appear before a sequence of 3 instructions.
|
|
|
|
*/
|
|
|
|
constexpr bool IsSchedInstruction(u32 offset, u32 main_offset) {
|
|
|
|
constexpr u32 SchedPeriod = 4;
|
|
|
|
u32 absolute_offset = offset - main_offset;
|
|
|
|
|
|
|
|
return (absolute_offset % SchedPeriod) == 0;
|
|
|
|
}
|
|
|
|
|
2018-12-20 22:39:46 -08:00
|
|
|
} // namespace
|
|
|
|
|
2018-12-20 14:09:21 -08:00
|
|
|
void ShaderIR::Decode() {
|
|
|
|
std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
|
|
|
|
|
2019-06-25 10:03:51 -07:00
|
|
|
disable_flow_stack = false;
|
2019-06-29 11:01:44 -07:00
|
|
|
const auto info = ScanFlow(program_code, program_size, main_offset);
|
2019-06-25 17:40:38 -07:00
|
|
|
if (info) {
|
|
|
|
const auto& shader_info = *info;
|
2019-06-24 16:46:49 -07:00
|
|
|
coverage_begin = shader_info.start;
|
|
|
|
coverage_end = shader_info.end;
|
|
|
|
if (shader_info.decompilable) {
|
2019-06-25 10:03:51 -07:00
|
|
|
disable_flow_stack = true;
|
2019-07-16 07:37:11 -07:00
|
|
|
const auto insert_block = [this](NodeBlock& nodes, u32 label) {
|
2019-06-25 10:03:51 -07:00
|
|
|
if (label == exit_branch) {
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
basic_blocks.insert({label, nodes});
|
2019-07-16 07:37:11 -07:00
|
|
|
};
|
2019-06-25 17:40:38 -07:00
|
|
|
const auto& blocks = shader_info.blocks;
|
2019-06-25 10:03:51 -07:00
|
|
|
NodeBlock current_block;
|
|
|
|
u32 current_label = exit_branch;
|
2019-06-25 08:10:45 -07:00
|
|
|
for (auto& block : blocks) {
|
2019-06-25 10:03:51 -07:00
|
|
|
if (shader_info.labels.count(block.start) != 0) {
|
|
|
|
insert_block(current_block, current_label);
|
|
|
|
current_block.clear();
|
|
|
|
current_label = block.start;
|
|
|
|
}
|
2019-06-25 08:10:45 -07:00
|
|
|
if (!block.ignore_branch) {
|
2019-06-25 10:03:51 -07:00
|
|
|
DecodeRangeInner(current_block, block.start, block.end);
|
|
|
|
InsertControlFlow(current_block, block);
|
2019-06-25 08:10:45 -07:00
|
|
|
} else {
|
2019-06-25 10:03:51 -07:00
|
|
|
DecodeRangeInner(current_block, block.start, block.end + 1);
|
2019-06-25 08:10:45 -07:00
|
|
|
}
|
|
|
|
}
|
2019-06-25 10:03:51 -07:00
|
|
|
insert_block(current_block, current_label);
|
2019-06-24 16:46:49 -07:00
|
|
|
return;
|
|
|
|
}
|
2019-06-25 10:03:51 -07:00
|
|
|
LOG_WARNING(HW_GPU, "Flow Stack Removing Failed! Falling back to old method");
|
2019-06-24 16:46:49 -07:00
|
|
|
// we can't decompile it, fallback to standard method
|
|
|
|
for (const auto& block : shader_info.blocks) {
|
|
|
|
basic_blocks.insert({block.start, DecodeRange(block.start, block.end + 1)});
|
|
|
|
}
|
2018-12-20 14:09:21 -08:00
|
|
|
return;
|
|
|
|
}
|
2019-06-25 10:03:51 -07:00
|
|
|
LOG_WARNING(HW_GPU, "Flow Analysis Failed! Falling back to brute force compiling");
|
2019-06-24 16:46:49 -07:00
|
|
|
|
|
|
|
// Now we need to deal with an undecompilable shader. We need to brute force
|
|
|
|
// a shader that captures every position.
|
2019-06-25 17:40:38 -07:00
|
|
|
coverage_begin = main_offset;
|
2019-06-25 04:57:32 -07:00
|
|
|
const u32 shader_end = static_cast<u32>(program_size / sizeof(u64));
|
2019-06-24 16:46:49 -07:00
|
|
|
coverage_end = shader_end;
|
|
|
|
for (u32 label = main_offset; label < shader_end; label++) {
|
|
|
|
basic_blocks.insert({label, DecodeRange(label, label + 1)});
|
2018-12-20 14:09:21 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-01-29 21:09:40 -08:00
|
|
|
NodeBlock ShaderIR::DecodeRange(u32 begin, u32 end) {
|
|
|
|
NodeBlock basic_block;
|
2019-06-25 10:03:51 -07:00
|
|
|
DecodeRangeInner(basic_block, begin, end);
|
|
|
|
return basic_block;
|
|
|
|
}
|
|
|
|
|
|
|
|
void ShaderIR::DecodeRangeInner(NodeBlock& bb, u32 begin, u32 end) {
|
2018-12-20 14:09:21 -08:00
|
|
|
for (u32 pc = begin; pc < (begin > end ? MAX_PROGRAM_LENGTH : end);) {
|
2019-06-25 10:03:51 -07:00
|
|
|
pc = DecodeInstr(bb, pc);
|
2018-12-20 14:09:21 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-06-25 08:10:45 -07:00
|
|
|
void ShaderIR::InsertControlFlow(NodeBlock& bb, const ShaderBlock& block) {
|
2019-07-16 07:37:11 -07:00
|
|
|
const auto apply_conditions = [&](const Condition& cond, Node n) -> Node {
|
2019-06-25 08:10:45 -07:00
|
|
|
Node result = n;
|
|
|
|
if (cond.cc != ConditionCode::T) {
|
|
|
|
result = Conditional(GetConditionCode(cond.cc), {result});
|
|
|
|
}
|
|
|
|
if (cond.predicate != Pred::UnusedIndex) {
|
|
|
|
u32 pred = static_cast<u32>(cond.predicate);
|
2019-06-25 17:15:40 -07:00
|
|
|
const bool is_neg = pred > 7;
|
|
|
|
if (is_neg) {
|
2019-06-25 08:10:45 -07:00
|
|
|
pred -= 8;
|
2019-06-25 17:15:40 -07:00
|
|
|
}
|
2019-06-25 08:10:45 -07:00
|
|
|
result = Conditional(GetPredicate(pred, is_neg), {result});
|
|
|
|
}
|
|
|
|
return result;
|
2019-07-16 07:37:11 -07:00
|
|
|
};
|
2019-06-25 08:10:45 -07:00
|
|
|
if (block.branch.address < 0) {
|
|
|
|
if (block.branch.kills) {
|
|
|
|
Node n = Operation(OperationCode::Discard);
|
|
|
|
n = apply_conditions(block.branch.cond, n);
|
|
|
|
bb.push_back(n);
|
|
|
|
global_code.push_back(n);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
Node n = Operation(OperationCode::Exit);
|
|
|
|
n = apply_conditions(block.branch.cond, n);
|
|
|
|
bb.push_back(n);
|
|
|
|
global_code.push_back(n);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
Node n = Operation(OperationCode::Branch, Immediate(block.branch.address));
|
|
|
|
n = apply_conditions(block.branch.cond, n);
|
|
|
|
bb.push_back(n);
|
|
|
|
global_code.push_back(n);
|
|
|
|
}
|
|
|
|
|
2019-01-29 21:09:40 -08:00
|
|
|
u32 ShaderIR::DecodeInstr(NodeBlock& bb, u32 pc) {
|
2018-12-20 14:09:21 -08:00
|
|
|
// Ignore sched instructions when generating code.
|
|
|
|
if (IsSchedInstruction(pc, main_offset)) {
|
|
|
|
return pc + 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
const Instruction instr = {program_code[pc]};
|
|
|
|
const auto opcode = OpCode::Decode(instr);
|
2019-07-05 11:13:14 -07:00
|
|
|
const u32 nv_address = ConvertAddressToNvidiaSpace(pc);
|
2018-12-20 14:09:21 -08:00
|
|
|
|
|
|
|
// Decoding failure
|
|
|
|
if (!opcode) {
|
|
|
|
UNIMPLEMENTED_MSG("Unhandled instruction: {0:x}", instr.value);
|
2019-07-05 11:13:14 -07:00
|
|
|
bb.push_back(Comment(fmt::format("{:05x} Unimplemented Shader instruction (0x{:016x})",
|
|
|
|
nv_address, instr.value)));
|
2018-12-20 14:09:21 -08:00
|
|
|
return pc + 1;
|
|
|
|
}
|
|
|
|
|
2019-07-05 11:13:14 -07:00
|
|
|
bb.push_back(Comment(
|
|
|
|
fmt::format("{:05x} {} (0x{:016x})", nv_address, opcode->get().GetName(), instr.value)));
|
2018-12-20 14:09:21 -08:00
|
|
|
|
|
|
|
using Tegra::Shader::Pred;
|
|
|
|
UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute,
|
|
|
|
"NeverExecute predicate not implemented");
|
|
|
|
|
2019-01-29 21:09:40 -08:00
|
|
|
static const std::map<OpCode::Type, u32 (ShaderIR::*)(NodeBlock&, u32)> decoders = {
|
|
|
|
{OpCode::Type::Arithmetic, &ShaderIR::DecodeArithmetic},
|
|
|
|
{OpCode::Type::ArithmeticImmediate, &ShaderIR::DecodeArithmeticImmediate},
|
|
|
|
{OpCode::Type::Bfe, &ShaderIR::DecodeBfe},
|
|
|
|
{OpCode::Type::Bfi, &ShaderIR::DecodeBfi},
|
|
|
|
{OpCode::Type::Shift, &ShaderIR::DecodeShift},
|
|
|
|
{OpCode::Type::ArithmeticInteger, &ShaderIR::DecodeArithmeticInteger},
|
|
|
|
{OpCode::Type::ArithmeticIntegerImmediate, &ShaderIR::DecodeArithmeticIntegerImmediate},
|
|
|
|
{OpCode::Type::ArithmeticHalf, &ShaderIR::DecodeArithmeticHalf},
|
|
|
|
{OpCode::Type::ArithmeticHalfImmediate, &ShaderIR::DecodeArithmeticHalfImmediate},
|
|
|
|
{OpCode::Type::Ffma, &ShaderIR::DecodeFfma},
|
|
|
|
{OpCode::Type::Hfma2, &ShaderIR::DecodeHfma2},
|
|
|
|
{OpCode::Type::Conversion, &ShaderIR::DecodeConversion},
|
|
|
|
{OpCode::Type::Memory, &ShaderIR::DecodeMemory},
|
2019-02-21 21:19:45 -08:00
|
|
|
{OpCode::Type::Texture, &ShaderIR::DecodeTexture},
|
2019-04-26 22:07:18 -07:00
|
|
|
{OpCode::Type::Image, &ShaderIR::DecodeImage},
|
2019-01-29 21:09:40 -08:00
|
|
|
{OpCode::Type::FloatSetPredicate, &ShaderIR::DecodeFloatSetPredicate},
|
|
|
|
{OpCode::Type::IntegerSetPredicate, &ShaderIR::DecodeIntegerSetPredicate},
|
|
|
|
{OpCode::Type::HalfSetPredicate, &ShaderIR::DecodeHalfSetPredicate},
|
|
|
|
{OpCode::Type::PredicateSetRegister, &ShaderIR::DecodePredicateSetRegister},
|
|
|
|
{OpCode::Type::PredicateSetPredicate, &ShaderIR::DecodePredicateSetPredicate},
|
|
|
|
{OpCode::Type::RegisterSetPredicate, &ShaderIR::DecodeRegisterSetPredicate},
|
|
|
|
{OpCode::Type::FloatSet, &ShaderIR::DecodeFloatSet},
|
|
|
|
{OpCode::Type::IntegerSet, &ShaderIR::DecodeIntegerSet},
|
|
|
|
{OpCode::Type::HalfSet, &ShaderIR::DecodeHalfSet},
|
|
|
|
{OpCode::Type::Video, &ShaderIR::DecodeVideo},
|
|
|
|
{OpCode::Type::Xmad, &ShaderIR::DecodeXmad},
|
|
|
|
};
|
2018-12-28 15:00:36 -08:00
|
|
|
|
|
|
|
std::vector<Node> tmp_block;
|
2018-12-20 14:09:21 -08:00
|
|
|
if (const auto decoder = decoders.find(opcode->get().GetType()); decoder != decoders.end()) {
|
2019-01-29 20:56:33 -08:00
|
|
|
pc = (this->*decoder->second)(tmp_block, pc);
|
2018-12-20 14:09:21 -08:00
|
|
|
} else {
|
2019-01-29 20:56:33 -08:00
|
|
|
pc = DecodeOther(tmp_block, pc);
|
2018-12-20 14:09:21 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Some instructions (like SSY) don't have a predicate field, they are always unconditionally
|
|
|
|
// executed.
|
|
|
|
const bool can_be_predicated = OpCode::IsPredicatedInstruction(opcode->get().GetId());
|
|
|
|
const auto pred_index = static_cast<u32>(instr.pred.pred_index);
|
|
|
|
|
|
|
|
if (can_be_predicated && pred_index != static_cast<u32>(Pred::UnusedIndex)) {
|
2019-01-29 20:56:33 -08:00
|
|
|
const Node conditional =
|
|
|
|
Conditional(GetPredicate(pred_index, instr.negate_pred != 0), std::move(tmp_block));
|
|
|
|
global_code.push_back(conditional);
|
|
|
|
bb.push_back(conditional);
|
2018-12-20 14:09:21 -08:00
|
|
|
} else {
|
2018-12-28 15:00:36 -08:00
|
|
|
for (auto& node : tmp_block) {
|
2019-01-29 20:56:33 -08:00
|
|
|
global_code.push_back(node);
|
|
|
|
bb.push_back(node);
|
2018-12-20 14:09:21 -08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return pc + 1;
|
|
|
|
}
|
|
|
|
|
2019-04-03 00:33:36 -07:00
|
|
|
} // namespace VideoCommon::Shader
|